Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Negative edge flip-flop with dual-port slave latch

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch Control signals RET and RETN determine when data is stored in the slave latch during retention mode

Secured master-slave D type flip-flop circuit

Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

A MOS approach to CMOS DET flip-flop design

Abstract: A novel approach to double-edge-triggered (DET) flip-flop design is presented along with a new static flip-flop and a new dynamic flipflop. The approach builds CMOS circuits using pass transistors and MOS-style clocked inverters and addresses issues of threshold voltage drop (V/sub T/ drop) and circuit complexity. Among DET designs, the number of switched and total transistors used by our flip-flops is less than or equal to any in related work. Our circuits beat all others in speed (maximum frequency response) by significant margins at medium to high supply voltages. The speed outperformance range for our static flip-flop is 1.5 to 5 V and for our dynamic flip-flop is <2.5 to 5 V.

High-speed operation of a resonant tunneling flip-flop circuit employing a MOBILE (monostable-bistable transition logic element)

Abstract: Resonant tunneling (RT) devices attract much attention because of their potential for high-speed operation as well as their high functionality, which leads to lower power dissipation. We have developed a highly functional logic gate, called MOBILE (monostable-bistable transition logic element), which exploits the negative differential resistance (NDR) of the RT phenomenon. In this paper, we demonstrate the high-speed operation-up to 18 Gb/s-of the MOBILE flip-flop (FF) circuit at room temperature. The present result indicates the promise of MOBILE-based FF circuits for high-speed digital applications.

On-chip probe circuit for detecting faults in an FPGA

Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.