Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
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TL;DR: In this paper, the authors proposed a method of calculating the switching probability of a high-Tc RSFQ logic circuit based on the Fokker-Planck equation.
Abstract: A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.
9 citations
Patent•
12 Nov 1969TL;DR: In this article, the authors proposed an approach to solve the JK-type FLIP-FLOP problem using only direct-coupleded logic gates, which can be used to simulate a state response.
Abstract: UNLOCKED JK-TYPE FLIP-FLOP USING ONLY DIRECT-COUPLED LOGIC GATES. ACTIVATING SIGNALS APPLIED TO EITHER OF TWO INPUTS CAUSE THE FLIP-FLOP TO ASSUME A STATE CORRESPONDING TO THE ACTIVATED INPUT. ACTIVATING SIGNALS APPLIED TO BOTH INPUTS SIMULTANEOUSLY CAUSE THE FLIP-FLOP TO CHANGE STATE.
9 citations
Patent•
NEC1
TL;DR: In this article, a phase-delaying clock output from a voltage controlled oscillator by a predetermined phase is captured by a flip flop, and the clock is then detected when out-of-sync.
Abstract: The circuit includes a delay circuit 1 for phase-delaying clocks output from a voltage controlled oscillator by a predetermined phase, a flip flop 2 for capturing the clock delayed by the delay circuit at a falling edge or rising edge of the data signal, an average value circuit 3 for detecting a time average value of an output of the flip flop, and a comparator 4 for comparing in amplitude the time average value with a predetermined fixed value and then issuing an alarm when out-of-sync of a clock is detected.
8 citations
Patent•
14 Nov 2001TL;DR: A scan flip flop with a selector is inserted into a position on a path where a timing error has occurred, based on timing analysis in a logic BIST mode, so that the path where the timing error occurred is pipelined as discussed by the authors.
Abstract: A scan flip flop with a selector is inserted into a position on a path where a timing error has occurred, based on timing analysis in a logic BIST mode, so that the path where the timing error has occurred is pipelined.
8 citations
23 Jul 2013
TL;DR: A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented that can be fabricated by standard CMOS process with a 2-ploy layer.
Abstract: A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode quaternary flip-flop is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported quaternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.
8 citations