Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption by controlling a switch circuit inserted between an input data node and a latch circuit for holding data so as to be conducted for a prescribed period at the time of the rise and fall of clock signals. SOLUTION: The delay of the clock signals CKY is larger than the delay of the clock signals CKX and a period when both CKX and CKY become an 'H' level is present at the time of both rise and fall of the clock signals CK. Since all serially connected transistors 25, 26, 27 and 28 are conducted in the period, the normal, and reverse signals of input data are passed through the switch circuit 18 and inputted to the latch circuit 13. Since the latch circuit 13 fetches the input data at the time of both rise and fall of the clock signals CK, this flip-flop circuit is operated at a speed which is the double of the frequency of the clock signals CK. Thus, a clock frequency is reduced by half and the power consumption is reduced.

Design of a low-power pulse-triggered flip-flop with conditional clock technique

Abstract: Flip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is designed. In CCFF, the clock is blocked when the input remains unchanged so that the internal nodes will not switch with the clock, which reduces the power consumption effectively. Based on the TSMC 0.18μm technology, the post-layout simulation results show that the proposed CCFF has an obvious advantage in power consumption when the data switching activity factor is below 50% as compared with other state-of-the-art pulse-triggered flip-flops, and the power saving is more than 50% when the activity factor is 10%.

Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power for Low Data Activity Applications

Abstract: In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The proposed clock-gating scheme only requires 4 transistors, thus occupies the small silicon area. Further, the proposed clock gating network can be shared among a group of flip-flops to reduce the power and area overhead of the gating network. The simulation results show that for all supply voltages, the proposed flip-flop has the least power dissipation among all the designs for low switching activities. The proposed flip-flop has up to 7.82 times power improvement than the existing flip-flops. However, for 100% data activity, the proposed FF consumes up to 2.71 times power than the existing flip-flops. The proposed clock gated flip-flop structure is best suited for applications where input signal switching activity is low and speed is not a crucial factor.

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Abstract: A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

High speed linear feedback shift register

Abstract: An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.