Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

A Novel Delayed Flip-Flop Circuit Using Resonant Tunneling Logic Gates

Abstract: A novel delayed flip-flop circuit using monostable-bistable transition logic elements (MOBILEs) was proposed, and was fabricated using resonant-tunneling-diode/high-electron-mobility-transistor integration technology on an InP substrate. Error free operations at up to 12.5 Gb/s were demonstrated at room temperature.

Latch circuit and master slave type flip-flop circuit

Abstract: PURPOSE:To obtain the latch circuit by which a high processing speed and low power consumption are attained. CONSTITUTION:A switching means 22 is conductive and input information is delivered to a node 3. In this case, a switching means 22 is conductive and the node 3 and a node 18 are electrically connected. When current input information is inverted preceding input information, a potential of the node 3 is quickly changed by the inverted information stored in a capacitive element 17 and the information based on the current input information is outputted to an output node 2. When a switching means 5 changes to the nonconductive state, the switching means 22 changes to the nonconducting state and the node 3 receives no effect of the capacitive element 17. In this case, the switching means 12 is conductive and the information of the node 11 is delivered to a latch section input node 3, a latch section 8 reaches the latch state, a switching means 19 is conductive and the information of the latch section output node 4 is delivered to the node 18 via the switching means 19 and the inverted information is stored in the capacitive element 17.

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Abstract: Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.

Semiconductor integrated circuit

Abstract: PURPOSE:To control a scan pass circuit without providing a control signal line exclusive for scan pass. CONSTITUTION:A semiconductor integrated circuit has a detecting means (a resistor 13, a capacitor 14, an inverter 15) for detecting the duty ratio of, the clock signal CK supplied to each flip flop 11 at conducting a control for switching the operation mode of a plurality of flip flops 11 connected in series to each other and arranged in the semiconductor integrated circuit into general operation mode and scan test mode; and a selector 12 for switching the operation mode of the flip flop 11 to general operation mode and scan test mode according to the output of the detecting means so that the switching between the scan test mode and the general operation mode is conducted according to the duty ratio of the clock signal CK. Thus, the state of each flip flop 11 can be set to the state according to a test object, and the circuit area can be contracted.