Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time

Abstract: A new current-mirror sense-amplifier based Flip-Flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed Flip-Flop at ultra-low voltage (down to 120mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the Pulse Generator stage as well as the delay of the Set-Reset (SR) Latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed Flip-Flop is implemented in a 65nm CMOS technology.

Asyncronous edge-triggered RS flip-flop circuit

Abstract: An edge triggered RS-type flip-flop circuit is disclosed which is capable of changing its state in response to a significant signal transition applied to a currently active input (SET or RESET) and independently of the current state of the other input (RESET or SET). The device can have one or more SET and RESET inputs, as well as Clear and Preset auxiliary inputs, and for the latter inputs the flip-flop circuit will behave as an ordinary RS flip-flop.

Logic circuit which can be selected to function as a d or t type flip-flop

Abstract: A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.

Pulsed static flip-flop

Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Double-edge Triggered Level Converter Flip-Flop with Feedback

Abstract: In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DE_LCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.