Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Circuit for coupling an event indication signal across asynchronous time domains

Abstract: A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal. Transparent latch circuitry latches the delayed event indication signal responsive to a latch control signal, and combination circuitry is coupled to receive the event indication signal and the result event indication signal, and provides a combination thereof as the latch control signal.

Semi-dynamic flip-flop with partially floating evaluation window

Abstract: Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors.

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint

Abstract: Clock network should be optimized to reduce clock power dissipation. The power efficient clock network can be constructed by multibit flip-flop generation and gated clock tree aware flip-flop clumping to pull flip-flops close to the same integrated clock gating cell. It is capable of providing an attractive solution to reduce clock power. This paper considers multicorner and multimode timing constraints for the two combined approach. This proposed method is applied to five industrial digital intellectual property blocks of state-of-the-art mobile system-on-a-chip fabricated in 14-nm CMOS process. Experimental results show that MBFF generation algorithm achieves 22% clock power reduction. Applying a gated clock tree aware flip-flop clumping on top of the MBFF generation further reduces the power to around 32%.

All-Optical counter based on optical flip-flop and optical AND gate

Abstract: An all-optical counter is presented using cascaded stages composed by SOA fiber laser based optical flip-flops and SOA four wave mixing AND logic gates. Two-bit all-optical pulse counting and optical frequency division are demonstrated.

Low area flip-flop with a shared inverter

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.