Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Adjustable hold flip flop and method for adjusting hold requirements

Abstract: A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.

Ultra compact non-volatile flip-flop for low power digital circuits based on hybrid CMOS/magnetic technology

Abstract: Complex systems are mainly integrated in CMOS technology, facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (over 1016) and immunity to radiations. Combined with CMOS devices they offer specific and new features to designs. Indeed, the emerging hybrid CMOS/Magnetic process allows integrating magnetic devices within digital circuits, modifying the current architectures, in order to contribute to solve the CMOS process issues. We present a high performance innovative non-volatile latch integrated into a flipflop which can operate at high speed. It can be used to design non-volatile logic circuits with ultra low-power consumption and new functionalities such as instant startup. This new flip-flop is integrated as a standard cell in a full Magnetic Process Design Kit (MPDK) allowing full custom and digital design of hybrid CMOS/Magnetic circuits using standard design tools.

Programmable sequence controller with counting function

Abstract: A programmable sequence controller with a counting function comprises an addressable latch circuit including at least one flip flop. A counter is connected to the flip flop such that the content of the counter is changed by one each time the flip flop is set. A setting device is provided for manually setting a count-up value of the counter. A comparator generates a count-up value signal when the counting-up of the counter to the count-up value is detected. A data selector is connected to receive the count-up value signal for supplying a logical value indicative of the status of the comparator. A logic operation circuit is responsive to a test command of a first instruction for testing a logical value of one of a plurality of external input devices and the data selector specified by address data in the first instruction and also responsive to an output command in a second instruction for generating an output command signal based upon the result of the test. The flip flop is set in response to the output command signal generated from the logic operation circuit when the flip flop is designated by the address data.

Positive Feed Back Adiabatic Logic: PFAL Single Edge Triggered Semi-Adiabatic D Flip Flop

Abstract: 2 Abstract: The technical constraints and market demands necessitated the urgency of efforts in development of low power circuits. Researchers are exploring all the different factors which affect the low power equations for the circuit. All these being realistic parameters have limits of their optimization. The device scaling, capacitance reduction, voltage scaling, activity factor improving using different set of encoding, speed performance constraints etc. have their physical limitations. Yet, their limiting values are near, but still debatable, with the progress of technology and tremendous amount of efforts all over the world by the researchers. In the scenario many researchers are trying to adopt different optimization and energy conservation principles for VLSI circuit design. The problem formulation is made in accordance, matching with the platform of other engineering fields and transforming, resolving and optimizing them to extract the desired power aware design with benefits attaining from the classical approach. Utilizing the concepts and fundamentals of adiabatic theory in mechanics for formulating the VLSI circuit design problems comes into such an efforts proposed and backed by several researchers. The basic principle in adiabatic logic circuits is to slow down the logic transition varying from logic 1 to logic 0 and vice versa, aiming in reducing the power dissipation. Many different approaches/ techniques are proposed for implementing adiabatic logic circuits. PFAL is one of these techniques which positively promise assisting in the power issues. This paper presents a dual rail, semi adiabatic PFAL D flip flop. Master slave configuration is used for implementing the positive edge flip flop. The basic buffer/inverter configuration is used for driving the functionality of the D flip flop after integrating extra transistors. Tanner ECAD tool is used for simulation and verification the circuit with 1.25 micron technology. The power dissipation for the circuit is 3.50E-02.

D flip-flop circuit

Abstract: PURPOSE:To provide the D flip-flop used to form a shift register surely latching a signal independently of the presence of skew in a clock signal. CONSTITUTION:A switch SW1 is closed with a clock CK set to a low level and an input signal D is latched by a latch circuit comprising inverters 3, 4. With the clock CK set to a high level, a switch SW2 is closed and an output of the inverter 3 is latched by a latch circuit comprising inverters 7, 8. An output of the inverter 7 is fed via a resistor R to an inverter 9, where it is inverted and further inverted by an inverter 10 and the result is outputted externally. The input signal to the inverter 9 is delayed sufficiently from the clock outputted from an inverter 12 by the action of the resistance. R and the capacitance of the input section of the inverter 9, then no latch mistake takes place due to a skew in the clock signal in the shift register comprising lots of connection of the D flip-flop circuits as above.