Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Set-reset flip-flop

Abstract: A circuit for setting and resetting a bistable circuit includes first and second transistors directly connected to the input of the bistable circuit for selectively clamping the input to a first or a second voltage level for setting the bistable circuit to one state or resetting it to the other state. In a bistable circuit comprised of a master flip-flop coupled to a slave flipflop by a transmission fate, the set-reset circuit includes first and second transistors directly connected to the input of the master and also includes means for enabling said transmission gate concurrently with the torn on of said first or second transistors for transferring the output of the master to the slave.

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

Abstract: In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual $V_{{\mathrm{DD}}}$ design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power-delay product (PDP). A TSMC 90-nm CMOS process was selected as the implementation technology. In this paper, the performance levels of seven FF designs were compared. The timing parameters of each FF were first characterized. Post-layout simulation results indicated that the proposed design excelled in various performance indices such as PDP, clock-to-Q delay, average power consumption, and leakage power consumption. Moreover, the design was determined to have the smallest layout area. Compared with the conventional transmission-gate-based FF design, the PDP improvement in the proposed design was up to 63.5% (at 12.5% switching activity) and the area saving was approximately 10%. Further simulations on process corners, supply voltage settings, and working frequencies were conducted to study the design reliability.

Double data rate flip-flop

Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

Flip-flop circuit having low power data retention

Abstract: A flip-flop ( 10 ) has a normal mode and a low power mode to save power. The flip-flop ( 10 ) has a master latch ( 14 ) and a slave latch ( 20 ). The slave latch ( 20 ) is used to retain the condition of the flip-flop ( 10 ) during the low power mode, where power is withdrawn from the master latch ( 14 ) but maintained on the slave latch ( 20 ). The slave latch ( 20 ) may use transistors with lower leakage characteristics than the transistors that make up the master latch ( 14 ). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop ( 10 ) is maintained by implementing the slave latch ( 20 ) so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch ( 20 ) has an input/output terminal to tap into the signal path between the master latch and an output circuit ( 22 ).

Flip-flop circuit having transfer gate delay

Abstract: The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.