Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Abstract: We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks.

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model

Abstract: A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

Abstract: A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2- mu m-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well. >

Igfet flip-flop having facility for forcing its state

Abstract: A bi-stable flip-flop circuit utilizing insulated gate field effect transistors in a plurality of logic circuits connected to receive a bi-level signal and the inverse thereof on two inputs and to supply an output signal and the inverse thereof on two outputs, the outputs being of a frequency of one-half of the frequency of the input signals. The output signal and the inverse thereof can be forced to a predetermined binary value and the inverse thereof by the application of a state-forcing signal, irrespective of the input signals.

Adiabatic Two-Phase CPAL Flip-Flops Operating on Near-Threshold and Super-Threshold Regions

Abstract: Low-power adiabatic flip-flops operating on near-threshold and super-threshold regions are investigated in this paper. The flip- flops are realized using two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. A traffic light controller operating on near-threshold and super- threshold regions is verified. All circuits are simulated using NCSU PDK 45 nm technology by varying supply voltage from 0.4 V to 0.9 V with 0.1 V steps. Based on the HSPICE simulation results, the energy consumption of the medium-voltage adiabatic flip-flops using two-phase CPAL circuits can be greatly reduced with reasonable speed.