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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


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Patent
10 Jul 1980
TL;DR: In this article, a passive delay line is used to delay the incoming signal whilst a bypass path directs an undelayed signal directly to the input of an exclusive OR gate, the delayed input is presented to the other gate input.
Abstract: Circuitry is for recovery of clock pulses from an incoming data transmission so that the clock pulses can be used for synchronising a decoder, esp. applicable to Bi-phase coded transmissions. A passive delay line delays the incoming signal whilst a by-pass path directs an undelayed signal directly to the input of an exclusive OR gate, the delayed input is presented to the other gate input. The gate output operates the set input of a counter and the recovered clock pulse is taken from the output. The delay line comprises two NAND gates (1, 4) and RC circuitry (2, 3, 5, 6). The delayed and undelayed signals are input to an Exclusive OR gate (7) with its output fed to a NAND gate (8) with a feedback from the counter (9). The NAND gate (8) output is used to set the counter (9). The D type Flip Flop (12) delays the incoming data (E) so that it is available at the output (A2) with reconstituted clock pulse and in sync with the clock pulse at the other output (A1).

7 citations

Patent
02 Jun 1983
TL;DR: In this paper, a flip-flop is provided having a data gate circuit for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data.
Abstract: A flip-flop is provided having a data gate circuit means (1) for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit means (2) is coupled to the data gate circuit means for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit means (3) is coupled to the master circuit means for storing the internal data signals. A reset means (23) supplies a synchronous reset signal to the master circuit means for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.

7 citations

Patent
28 Apr 1995
TL;DR: In this paper, a first and second gated SR (set-reset) latches are used to represent a first pulse signal to the S1 input of the first latch and an inverted representation of a second pulse signal at the second latch, whereby timed output signals representing a differential between the leading edges of the two signals are provided at the outputs of the outputs Q, QN.
Abstract: A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.

7 citations

Patent
10 Sep 2001
TL;DR: In this paper, the complementary outputs of a master slave flip flop are made symmetric, with substantially zero timing skew over all process, voltage and temperature conditions, by utilizing a master latch and a pair of identical slave latches.
Abstract: The complementary outputs of a master slave flip flop are made symmetric, with substantially zero timing skew over all process, voltage and temperature conditions. This is accomplished by utilizing a master latch and a pair of identical slave latches. Although the complementary outputs from the master latch have non-zero timing skew when the clock goes low, they have zero timing skew when the clock goes high. Thus the identical slave latches, whose outputs react to the master latch outputs only when the clock goes high, do not have any timing skew.

7 citations

Journal ArticleDOI
TL;DR: In this paper, a dual-gate AlGaN/GaN E-HEMT was proposed for GaN-based digital ICs, where the NAND gate and D flip-flop were demonstrated in a GaN system for the first time.
Abstract: Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.

7 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868