Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Function clock generating circuit, and d flip-flop with enable function and storage circuit using the same

Abstract: PROBLEM TO BE SOLVED: To realize the function clock generating circuit in which a wiring area, a cell area and power consumption are reduced and design of timing is facilitated. SOLUTION: An input terminal D of a through-latch circuit LTC11 is connected to an input line of an enable signal EN, an inverted clock input terminal G is connected to an input line of a clock signal CK and one input terminal of a NAND gate NAND11 connects to an output terminal Q of the through-latch circuit LTC11, the other input terminal is connected to an input terminal of the clock signal CK and the output terminal is connected to an input terminal of an inverter INV11. Then the enable signal EN is sampled in the through-latch circuit LTC11 at a rising point of time of the clock signal CK and a logic gate LGT consisting of the NAND gate NAND11 and the inverter INV11 passes or blocks a clock pulse just after sampling depending on the sampled enable signal EN.

Compact GaAs HEMT D flip-flop for the integration of a SAR MMIC core-chip digital control logic

Abstract: The paper presents a novel, ultra-compact, reduced-area implementation of a D-type flip-flop using the GaAs Enhancement-Depletion (ED) PHEMT process of the OMMIC with the gate metal layout modified, at the device process level. The D cell has been developed as the building block of a serial to parallel 13-bit shifter embedded within an integrated core-chip for satellite X band SAR applications, but can be exploited for a wide set of logical GaAs-based applications. The novel D cell design, based on the Enhancement-Depletion Super-Buffer (EDSB) logical family, allows for an area reduction of about 20%, with respect to the conventional design, and simplified interconnections. Design rules have been developed to optimize the cell performances. Measured and simulated NOR transfer characteristics show good agreement. A dedicated layout for RF probing has been developed to test the D-type flip-flop behaviour and performances.

Low power D flip-flop serial in/parallel out based shift register

Abstract: The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design. The flip-flops (FF's) consumption of casual logic power in a SoC chip (system on chip) commonly overpasses 50% as long the input and the output are in the same state thanks to the redundancy transition of interior loops. Conventional implementation of shift register systems such as linear feedback shift registers (LFSR) have two main drawbacks namely that elements into structure have been clocked during every clock cycle, and throughput is confined to just one (1) bit per clock cycle. Large scale integrated systems have much higher power consumption when tested due to the increased level of circuit activity. The higher rate of circuit activity can help reduce transition times that are from the input to the output phases. Flip-flops have been performed in 0.18μm CMOS technology. Circuit simulations with displays showing appropriate power dissipations have been reduced are possible where input signals decrease switching activities. A 16-Bit shift register is shown as an easy low power usage.

Method and machine for scrambling parallel data channels

Abstract: A method and system for generating a pseudo-random bit series based on a given polynomial of order N, for M parallel communication lines using a machine comprising: N flip-flop machines and logic circuit. The flip-flop machines is initialized according to a given series of N bits. The logic circuit calculates a series of the next M+N tits using the N flip flop machines as function of the current N bit series wherein the function is based on two pre-generated equations. These equations are generated by recursive calculation of matrix array of order N*M according the given polynomial equation.

Non-contact ic card and non-contact ic card system

Abstract: PROBLEM TO BE SOLVED: To stably execute the operation of the internal circuits by providing a reset generation circuit in the non-contact IC card operate various internal circuits only when power voltage for an operation in a non-contact card is more than a prescirbed value. SOLUTION: Since the input of a flip flop 45 is almost equal to VDD until time when VDD reaches 5V from the reception start time of a radio wave, a reset being the output is almost equal to VDD and the internal circuits are reset during that period. At time when VDD reaches 5V of the operation voltage of the internal circuits, a regulation circuit 33 operates, the output signal is dropped from 'H' to 'L' and the output of a NAND gate 47 goes to 'H'. The voltage VDD point B is impressed on one input of a NAND gate 46, and the 'H'-level of the output of the NAND gate 47 is impressed on the other input. Thus, the output of the NAND gate 46 becomes 'L', and a reset state is released.