Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit (LSI) in which timing design is easily performed, and any timing error is prevented when transferring data between a plurality of the LSI. SOLUTION: This semiconductor integrated circuit is provided with a first flip flop group 13 just after an input port, a second flip flop group 14 just before an output port, a third flip flop group 15 in the circuit, a first clock distributing means 16 for supplying a reference clock to the first flip flop group 13 while making almost constant the delay quantity of the reference clock signal, a second clock distributing means 17 for supplying the reference clock signal to the second flip flop group 14 while making almost constant the delay quantity of the reference clock signal, and a third clock distributing means 18 for supplying the reference clock signal to the third flip flop group 15 while making almost constant the delay quantity of the reference clock signal. In this case, the delay time of the first clock distributing means 16 is set so as to be made larger than the delay time of the third clock distributing means 18, and the delay time of the second clock distributing means 17 is set so as to be made smaller than the delay time of the third clock distributing means 18.

S-R flip-flop circuit

Abstract: An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

Design and optimization of single and multiple-loop reversible and quantum feedback circuits

Abstract: The majority of work in reversible logic circuits has been limited to combinational logic. Researchers are now beginning to suggest designs for sequential circuits. In this paper we propose a new method to design and optimize feedback reversible logic circuits and a specific group of quantum logic circuits based on the reversible state transition table and genetic algorithms (GA). To show the efficiency of the proposed method, some reversible sequential elements such as D and T flip-flops (FFs), with and without clock and reset, and edge triggered FFs are designed. We have also extended our method to multiple loop feedback circuits. The proposed circuits are highly optimized using a GA synthesis tool that allows don't care values. Some of the designs in this paper are presented in other papers; however, the comparisons show that the quantum cost and number of garbage inputs/outputs are reduced efficiently by our method.

Optimized design and performance analysis of Johnson counter using 45 nm technology

Abstract: Sequential circuits largely contribute to the power dissipation and propagation delay in a digital system. Low power, less delay and area efficient sequential circuit design has been the major concern for VLSI designers. The selection of optimized design technology plays a key role in achieving the above parameters. A counter is a sequential circuit having wide application area in microcontroller circuits including PLL, Digital to Analog converters, signal generators, signal synthesizers etc. In this paper a low power, high speed and cost efficient 4 bit Johnson counter is proposed. Deployed flip flop circuit uses 14 transistors to realize the negative edge triggered master slave D flip flop operation. Performance and cost of the proposed counter is compared against the conventional counter. The proposed design is found 48.86 % faster with having 43.22 % lesser power dissipation than conventional design. The transistor requirements in the proposed counter is also 69.5 % lesser making it an optimized design in terms of area.