Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Clocked delay type flip flop

Abstract: 1,139,628. Transistor bistable circuits. MOTOROLA, Inc. 14 Nov., 1967 [16 Dec., 1966], No. 51829/67. Heading H3T. A bistable circuit comprises a master bistable circuit 9 with its outputs 35, 37 connected to a slave bistable circuit 7 and a clock circuit 6 which locks the master and enables the slave when applied clock signals are at one logical level, and which locks the slave and enables the master when the clock signals are at another logical level. Assume initially that the clock pulse C is at a low level, then transistor 82 is overidden by transistor 80 to enable transistor 74. With a low level input at AN, transistor 70 overides transistor 74 switching off transistor 56 to give a low level output at QM and switching on transister 58 to give a high level output at #QM. When clock C goes to its high level, transistor 88 switches on switching on transistor 82 to lock the master, and switching on transistor 34 to enable the slave. The high QM and low #QM inputs now set the slave to Q high and Q low. Reversion of clock C to its low level locks the slave in this state and enables the master to respond again to the A, R, or S inputs. A high A switches the master to QM high and #QM low. An input at S or R will set or reset both master and slave irrespective of the clock level. For example a high reset R will switch on transistor 28 slightly before transistor 34 thus resetting the slave. The various transistors are biased from a circuit 8 which includes temperature stabilizing diodes 96, 98.

Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture

Abstract: Phase frequency detector is one of the basic building blocks for Phase Locked Loop (PLL) architecture. The power efficient Delay flip-flop based Phase frequency detector topology is proposed with two parallel clocked latches by following twin latch parallel paradigm method. To construct the latching sections of the circuit, the power reduction techniques such as reducing the numbers of transistors and spilt path technique are incorporated, which leads to reduction of dynamic power and short circuit power consumption respectively. The twin latch paradigm method improves the performance of the system interms of speed due to the sampling of input data at both positive and negative edge arrival of the clock signal. The proposed topology is implemented in MICROWIND EDA tool and evaluated by simulating the circuit under 0.12µm CMOS process technology. The simulation infers that the proposed design achieves power saving from 28.57% to 33.82%, improvement of power energy product ( PEP) from 0.6% to 2.5% and Power area product (PAP) from 10.66% to 12.6% compared to conventional phase frequency detectors.

Design of a fully-static differential low-power CMOS flip-flop

Abstract: A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson (see IEEE Jour. of Solid-State Circuits, vol. 32, no. 1, p. 62-9, 1997) in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure is shown to consume less power and occupy a smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures.

System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop

Abstract: The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.