Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Design of high speed master-slave D-type flip-flop in InP DHBT technology

Abstract: In this paper, we present some design problems of the high speed master-slave D-type flip-flop (MS D-FF). Essential to long haul optical fiber communication systems, this circuit is critical since it operates at the highest clock frequency for a given bit rate. We discuss specific aspects of electrical design of such a circuit and underline some important points of the layout of gigabit circuits. The MS D-FF was fabricated in our self-aligned InP DHBT technology. On wafer measurements show correct operation at 40 Gb/s.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

Abstract: For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Random generator description

Abstract: A pseudo random generator comprising a shift register comprising a first flip flop (F0) and n further flip-flops (F1....Fn) each flip-flop (F0) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F0) having a set input, each of the non-inverting outputs being connected via a NOR gate (10) to the set input of the first flip-flop (F0) and each of the non-inverting outputs of the flip-flops (F0...Fn) being connected to the input of the first flip-flop (F0) via an XOR gate (11), characterised in that the generator comprises at least one additional logic gate (13, 14, 15; 17, 18, 19) including at least one additional flip-flop (14;18). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal.

Stochastic Computing Arrangement.

Abstract: 1,184,652. Stochastic computation. STANDARD TELEPHONES & CABLES Ltd. 3 March, 1967 [7 March, 1966], No. 9871/66. Headings G4A, G4D and G4G. [Also in Divisions G1 and G3] General.-A computer assembly comprises one or more digital computing elements, means for representing input information stochastically by the probability that a level in a clocked sequence of logic levels will be ON, means for applying the so represented information to the computing element(s) performing digital computation, and means for converting the stochastically represented outputs of the computation into analogue or digital information valves. Theory.-Analogue variables are presented as probabilities that a specific binary or multilevel event will occur (or generally the probability that a specific configuration representing one of several possible events will occur), and a quantity or event may be scaled as a probability 1 > P > 0, and represented by a sequence of logic levels or states of the inputs and outputs of the computer elements; which representation, e.g. by the adaptive device of Specification 1,099,574, is stochastic since the event or quantity is defined by the statistical properties of a sequence as to the probability that it represents a given event or quantity. In affine symmetric binary representation, analogue quantity -E 0, the states being permanently on or off for maximum or minimum values of V and randomly fluctuating therebetween (or OPEN) for zero. Thus V = [p (ON) - p (OFF)] E 9/ for a sequence in a ternary device wherein p (on) and p (off) are the relative frequencies of on and off conditions and for 0 0 is a scaling factor; Zero being represented by "OFF" and infinity by "ON" and extensible to negative quantities by multiplication by (- 1). In symmetric projective ternary representation, when V#0 and when V 1 = E - V for affine asymmetric binary representation, V 1 = - V for affine symmetric binary and ternary, projective symmetric ternary, hyperbolic ternary, and trigonometric 1 binary V 1 = - for projective binary represen- V tation. Fig. 6 shows a multiplication circuit for afline symmetric binary representation. If + denotes OR switching and juxtaposition indicates AND switching, while a superposed bar indicates a Boolean inverse so that a = 0 if and only if a = 1 a = 1 if and only if a = 0, the levels a, b as shown are applied through inverters to AND gate 1 as #a #b and directly to AND gate 2 as a, b, so that output of OR gate 3 is #a #b + ab which represents the scaled products of the variables represented by the sequences of a and b; the multiplier being an equality gate giving ON output if and only if its inputs are identical. For multiplication of further quantities, such multipliers are cascaded. An affine ternary representation multiplier is identical logically with that of Fig. 6 and (Fig. 1, o, p, not shown). For a multiplier in projective binary representation, a cross coupled flip flop FF (Fig. 3) receiving inputs X, Y is clocked to change over to a value dependent on its prior state and preceding inputs X, Y; the output Z from an OR gate energized from two AND gates receiving X, Y and the flip flop outputs being equal to a new input X if the flip flop output Q is ON, and equal to the complemented new input #Y if the Q input is ON. The device realizes the transformation For multiplication in projective binary representation (Fig. 4) a clocked cross coupled flip flop CCFF receives inputs AB, #AB from AND gates respectively energized from inputs A, B; directly and through inverters in synchronous logic, while in asynchronous logic the clock pulses may be obtained from a local oscillator, or triggered from a change of output if the inputs are mutually exclusive. A further delay flip flop in one input acts as correlation isolator (Fig. 7, not shown). For evaluation of squares and higher powers utilizing plural multipliers, input isolators utilizing clock pulse delay flip flops (Figs. 7, 8, not shown) are inserted to avoid autocorrelation of the inputs, whenever identical signals are applied to multiple paths, in stochastic computation. Autocorrelated sequences may be de-correlated (Fig. 21) by introducing random delays whose maximum delay # autocorrelated depth from noise sources changing over triggers at random intervals to randomize the clock pulses of flip flops FF1, FF2 when the noise exceeds a predetermined level. The random states are transferred to flip flops FF3, FF4. Flip flops FF5, FF6, FF7 connected as a shift register to the direct inverted input hold previous input states at unit, two, and three delay intervals respectively, and flip flops FF3, FF4 gate one of these delayed inputs through three input AND gates and a common OR gate to the output line, so that at each clock pulse a random delayed replication of the input appears on the output. In an adder for symmetric and asymmetric binary affine representation (Fig. 9), a first flip flop FF is triggered from a noise source with grounded inputs, and its output is applied to a second flip flop FF emitting an ON level to AND gate 4 and an OFF level to AND gate 5, or vice versa with equal probability, so that the probability p (Z) of output from OR gate 6 is ¢ (PA + PB) from gates 4, 5. It is shown that the output is 1/k the sum of the inputs for a k input adder, and for 2 inputs a trigger pulse is applied to clock input of a first flip flop when signal from random noise source exceeds a preset threshold, to change its state, since its inputs are in a random condition at the instant of a clock pulse. Random sequences carrying information are generated in a comparator with binary output having a random first input and a fixed or variable second input responsive to input voltage or digital code; the random input containing all levels with equal probability. Fig. 10 shows analogue/stochastic converter generating random sequences comprising a comparator receiving an analogue input and an input from a digital to analogue converter triggered at T by a series of flip flops FF, each in turn triggered on its clock line from a random noise source exceeding a predetermined threshold. The flip flops are in random state so that the D/A converter feeds a random level to the comparator. If at a clock pulse applied to an output flip flop fed from the converter, the analogue input exceeds the random input, the output flip flop is ON and otherwise it is off, so that the output sequence is an affine binary stochastic representation of the analogue input if the D/A conversion is linear. Alternatively (Fig. 11, not shown) for digital input the latter is applied directly to a digital comparator also receiving the random digital output of a series of flip flops

Ultra-low power NAND based multiplexer and flip-flop

Abstract: Static power consumption has became a major problem as we are moving towards finer technologies Power consumption is one of the top concerns of VLSI circuit design, for which CMOS is the primary technology However, there is no universal way to avoid tradeoffs between power, delay and area, and thus designers are required to choose appropriate techniques that satisfy application and product needs We are presenting two low power digital circuits 4*1 multiplexer and JK master-slave flip-flop designed with ultra low power NAND gates These NAND gates have been designed with combination of sleepy stack technique with reverse body bias (RBB) and dual threshold CMOS (DTCMOS) On comparison with conventional 4*1 multiplexer we have achieved maximum of 30% decrement in dynamic power consumption and 59% decrement in power consumption when circuit is in ideal state This all is achieved on the coast of 55% increment in worst case propagation delay For JK master-slave flip-flop we are achieving 13% reduction in dynamic power consumption and 99% saving in static power consumption All simulations have been done on 65nm technology with dual threshold transistors