Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology

Abstract: In this paper, a new flip flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads to a higher operational speed and lower power consumption compared to the previously proposed flip-flops. The results of the simulation show that the PDP of the proposed flip flop is reduced by at least 58.3%.

Skewness adjusting device for timing signal and its method

Abstract: PURPOSE: To form a skewness adjusting device capable of minimizing the fluctuation of the delay time in a timing signal supplying route in a high speed digital circuit operated by the timing signal of a high frequency. CONSTITUTION: At the time of selecting the input terminal 11 of a selector 50, a loop circuit including input buffer circuits 46-1, 46-2 and an output buffer circuit 51 is formed. At the time of selecting an input terminal I2, a loop circuit including the input buffer circuit 46-1 and the output buffer circuit 51 is formed and at the time of selecting an input terminal 13, a loop circuit including the input buffer circuit 46-1, a variable delay time generation circuit (VDL) 48 and the output buffer circuit 51. The delay time of each signal of them is obtained from the oscillation frequency of each loop circuit formed as a ring oscillation circuit. If the characteristics of the input buffer circuits 46-1 and 46-2 are made uniform, the delay time of the timing signal supplying route including the input buffer circuit 46-1 and VDL 48 to a flip flop(FF) 49 is correctly obtained by the mutual arithmetic operation of the signal delay time of each loop circuit. COPYRIGHT: (C)1995,JPO

Flip-flop including keeper circuit

Abstract: A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

Abstract: The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.

Flip-flop for scanning

Abstract: PROBLEM TO BE SOLVED: To provide a scanning flip-flop which operates at a higher speed by suppressing the increase in delay times by adding a test circuit. SOLUTION: The master slave-type scan flip-flop, used for the test of a semiconductor integrated circuit device and temporarily holding an input signal, has a first scan control part receiving the output signal of a master latch part synchronized and output to a scan clock which is a test clock during testing; a clock control part for receiving the output signal of the first scan control part, synchronized with a prescribed clock during normal operation and output to a slew latch part; and a second scan control part for connecting input to the output of the first scan control part and synchronizing and outputting a scan-out signal, corresponding to a scan-in signal which is an input signal for the test during the test to the scan clock.