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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the thermal behavior up to 300oC of 4H-SiC logic gates library is investigated. And the authors present new experimental results showing the thermal behaviour up to 30oC for 4H logic gates with epitaxial resistors and MESFETs.
Abstract: Due to our demonstrated stable Tungsten-Schottky barrier at elevated temperatures, and also thanks to our technological process maturity regarding SiC-Schottky contact fabrication, we have implemented the digital logic gates library adopting a normally-on MESFET topology. In this paper we present new experimental results showing the thermal behavior up to 300oC of 4H-SiC logic gates library, monolithically integrating normally-on MESFETs and epitaxial resistors. The implemented SiC devices are based on important CMOS features and are specially designed for large ICs device integration density.

5 citations

Journal ArticleDOI
01 Aug 2012-Optik
TL;DR: A novel concept of all-optical clocked flip-flop based on phase encoding process is proposed, where no switch is used in the main processing part of the unit and a real time operational speed is expected.

5 citations

Proceedings ArticleDOI
02 May 2011
TL;DR: In this paper, the authors use 3D TCAD simulations to model single-event related failures and develop mitigation techniques for flip-flop designs, as well as experimental results show validity of such an approach for future CMOS technologies.
Abstract: For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.

5 citations

Patent
Sylvain Clerc1
26 Oct 2005
TL;DR: In this article, a flip-flop device is provided that is triggered on the edges of a clock signal, which has an active mode in which it is electrically powered and an inactive mode.
Abstract: A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.

5 citations

Patent
Zuk Borys1
03 May 1977
TL;DR: In this article, a flip-flop consisting of two cross-coupled transistors each having one end of its main conduction path connected to a common current source, and in which switching between states is accomplished by the application of voltages coupled through voltage dropping resistors connected to the other ends of the main conduct paths of the two transistors.
Abstract: A flip-flop comprising two, cross-coupled, transistors each having one end of its main conduction path connected to a common current source, and in which switching between states is accomplished by the application of voltages coupled through voltage dropping resistors connected to the other ends of the main conduction paths of the two transistors. The circuitry for applying the switching voltages includes an emitter-coupled logic (ECL) gate comprising a differential amplifier stage containing a pulse forming network for producing a sampling pulse at one output and a clocking signal at another output. The sampling pulse is "AND'ed" with input data signals to set the flip-flop to one binary condition and the clocking signal is used to reset the flip-flop to the other binary condition. Circuitry for sensing the state of the flip-flop includes a differential stage whose inputs are coupled to the control electrodes of the transistors of the flip-flop.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868