Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
Papers published on a yearly basis
Papers
More filters
TL;DR: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme that is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities is proposed.
Abstract: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
5 citations
Proceedings Article•
20 Jun 2013TL;DR: Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performances in terms of average power and NED as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
Abstract: Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is breaking the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a fully dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover it will be shown that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performances in terms of average power and NED (Normalized Energy Deviation) as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
5 citations
Patent•
TSMC1
TL;DR: In this paper, an MCML retention latch and flip-flop are disclosed to reduce dynamic/static power consumption of MCML logic devices during power off mode, where a power switch is added to the master latch to power the slave latch off.
Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.
5 citations
TL;DR: In this work proposed design of SR flip-flop proved the compatibility of WSDAL for sequential logic also and the new designs perform well at stringent temperature conditions and can be used for low power electronics circuits.
Abstract: This paper presents a new architecture of energy recycling for low power applications. The reported design is based on the ultra-low-power diode Based on this concept, adiabatic logic inverter, a s...
5 citations
Patent•
03 Feb 2005
TL;DR: In this paper, a plurality of flip flop circuits driven by elements 101f of the last stages of a clock tree are mutually connected in series to constitute a subscan chain in order to suppress the power consumption by reducing the number of delay elements to be inserted to data lines of shift registers.
Abstract: PROBLEM TO BE SOLVED: To suppress the power consumption by considerably reducing the number of delay elements to be inserted to data lines of shift registers in order to secure a hold time in the shift operation of a scan shift register in scan test circuit design SOLUTION: A plurality of flip flop circuits (circuits 102a, circuits 102b, circuits 102c, etc) driven by elements 101f of the last stages are mutually connected in series to constitute a subscan chain in terms of element 101f of the last stage of a clock tree T Subscan chains between which the difference in the number of delay elements from a clock supply point S of the clock tree T is minimum (that is, the difference is one stage) are mutually connected Further, subscan chains are mutually connected so that data is shifted from flip flop circuits of long clock delay to flip flop circuits of short clock delay COPYRIGHT: (C)2005,JPO&NCIPI
5 citations