Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
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Patent•
22 Nov 2010
TL;DR: In this article, a signal multiplexing circuit (parallel/serial conversion circuit) which multiplexes, in time division manner, N pieces of low speed signals into a single high speed signal, in which, especially, a high speed clock is not used at the final stage of the circuit to abolish timing constraint was proposed.
Abstract: PROBLEM TO BE SOLVED: To provide a signal multiplexing circuit (parallel/serial conversion circuit) which multiplexes, in time division manner, N pieces of low speed signals into a single high speed signal, in which, especially, a high speed clock is not used at a final stage of the multiplexing circuit to abolish timing constraint.SOLUTION: By pre-coding, for example, a parallel signal by taking an exclusive OR between signals adjoining each other, the pre-coded parallel signal is delayed stepwise using flip flop. N pieces of signals, or delayed signal, are inputted into an exclusive OR circuit of N-input to generate an eventual serial output. Since, in this manner, the exclusive OR circuit at a final stage does not require input of a clock signal, the difficulty in timing design is eliminated, and further, no high speed clock is required, for reduced power consumption.
5 citations
Patent•
27 May 2013TL;DR: In this article, a flip-flop is used to store data when the IC is in built-in self-test (BIST) mode, where the data stored in the retention latch is transferred to the master latch.
Abstract: An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.
5 citations
TL;DR: In this paper, the authors describe a ternary flip-flop with three levels of voltage corresponding to logic status 2, 1, 0, when triggered by 1 kHZ pulses.
Abstract: The paper describes a Ternary flip-flop. The output is obtained in the form of three: levels of voltage corresponding to logic status 2, 1, 0, when triggered by 1 kHZ pulses.
5 citations
22 Nov 2015
TL;DR: A new transistor level scan cell design is proposed to eliminate the scan multiplexer off the functional path and thus in improving the timing performance of integrated circuits.
Abstract: The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.
5 citations
Patent•
07 Aug 2000
TL;DR: In this paper, a flip-flop for a semiconductor integrated circuit is provided with a delay/inverter means 410 for inputting a clock, delaying/inverting it, inputting first and second output signals and inverting these signals, a differential circuit means 400 and 420 for detecting and amplifying the signal level difference of positive and negative data signals being controlled by the clock and the output signal of the delaying or inverting means, and an S-R latch means 430 for outputting the output signals of the differential circuit.
Abstract: PROBLEM TO BE SOLVED: To provide a flip-flop capable of minimizing power consumption by preventing unwanted discharge without affecting an operating speed. SOLUTION: This flip-flop for a semiconductor integrated circuit is provided with a delay/inverter means 410 for inputting a clock, delaying/inverting it, inputting first and second output signals and inverting these signals, differential circuit means 400 and 420 for detecting and amplifying the signal level difference of positive and negative data signals being controlled by the clock and the output signal of the delaying/inverting means, and an S-R latch means 430 for inputting the output signals of the differential circuit means, latching these signals and outputting the first and second output signals. COPYRIGHT: (C)2002,JPO
5 citations