Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Timing yield enhancement through soft edge flip-flop based design

Abstract: The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13 mum CMOS. An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon useful-skew is applied).

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

Abstract: We propose a Bistable Cross-coupled Dual Modular Redundancy (BCDMR) Flip-Flop to enhance soft-error immunity. It is based on a BISER FF but its bistable cross-coupled structure enhances soft-error immunity without any area, delay and power overhead. We fabricated a 65nm LSI including 60,480bit shift registers with the BCDMR and BISER structures. Experimental results using α-particles reveals that the soft-error immunity of the BCDMR is enhanced by 150x at 160MHz clock frequency compared with the BISER.

Activity-sensitive flip-flop and latch selection for reduced energy

Abstract: This article presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We prepose the use of a selection of flip-flop latch designs, each timed for different activation patterns and speed requirements. We illustrate the use of our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by 60% without increasing cycle time.

Double-edge-triggered flip-flop providing two data transitions per clock cycle

Abstract: An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.

Design of D flip-flop and T flip-flop using Mach-Zehnder interferometers for high-speed communication.

Abstract: Electrical component speed is a major constraint in high-speed communications. To overcome this constraint, electrical components are now being replaced by optical components. The application of optical switching phenomena has been used to construct the design of the D flip-flop and T flip-flop based on the electro-optic effect in a Mach-Zehnder interferometer (MZI). The MZI structures show the powerful ability to switch the optical signal from one output port to the other. Hence, it is possible to construct some complex optical combinational digital circuits using the electro-optic-effect-based MZI structure as a basic building block. This paper constitutes the mathematical description of the proposed device and thereafter compilation using MATLAB. The study is carried out by simulating the proposed device with the beam propagation method.