Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
Papers published on a yearly basis
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TL;DR: In this article, the authors proposed a flip-flop circuit with a tri-state inverter and a master latch and a slave latch, and the data output selecting portion is constituted by two pass gates and an inverter connected to the output terminal.
Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.
34 citations
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TL;DR: Current mode logic and models and optimized design strategies for MUX, XOR, and D flip-flop are presented, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters.
Abstract: This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively.
34 citations
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18 Feb 2000TL;DR: In this paper, a combination non-volatile latch circuit with a bit signal and an inverse bit signal was presented. But the latch can be operated independently of the nonvolatile memory cells, and the contents of the latch could be stored in the memory cells.
Abstract: A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type having a first terminal, a second terminal and a control gate is supplied. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first voltage can be supplied to the second terminal of the first and second cells and a second voltage supplies a voltage to the control gate of the first and second cells. In this manner, the latch can be operated independently of the non-volatile memory cells, the status of the latch can be restored by the status of the non-volatile memory cells, and the contents of the latch can be stored in the non-volatile memory cells.
33 citations
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01 Jul 2005TL;DR: In this article, a master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer.
Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.
33 citations
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TL;DR: In this article, the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on lowvoltage organic thin-film transistors (TFTs) on flexible plastic substrates is presented.
33 citations