Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.

Method for distributing clock signals to flip-flop circuits

Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

Pulsed circuit topology including a pulsed, domino flip-flop

Abstract: A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology

Abstract: Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop.