Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
Papers published on a yearly basis
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TL;DR: This project moves around in replacing conventional master-slave based flip-flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications.
Abstract: Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. The concept of this project is to reduce the power consumption and to increase the speed and functionality of the chip. This project moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications. Initially in the critical path the pulse generation controls logic along with SVL function. A simple transistor SVL design is used to reduce the circuit complexity. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 180nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%. Index Terms-Flip-flop, low power,svl.
27 citations
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03 Apr 2006
TL;DR: In this paper, a D flip-flop with a half-static slave stage or a master stage with clock gating by the input and output is described. But the clock gated circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the inputs and outputs are at the same logical state.
Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.
27 citations
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TL;DR: In this article, the routing functionality of all-optical label swapping (AOLS) network is demonstrated in the frame of an alloptical logic gate and flip-flops.
Abstract: The routing functionality by all-optically interconnecting semiconductor-based all-optical logic gates and flip-flops is demonstrated in the frame of an all-optical label swapping (AOLS) network. We experimentally show that the output of the all-optical 2-bit correlator is capable of toggling the states of the integrated flip-flop every 2.5 ns via an adaptation stage. High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to complete the routing functionality of the AOLS node. The potential integration of these semiconductor optical amplifier integrated Mach-Zehnder interferometer-based devices make the proposed approach a very interesting solution for future packet switched optical networks.
27 citations
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TL;DR: In this paper, a flip-flop circuit using a resonant-tunnelling hot electron transistor (RHET) was proposed, which uses a resistor in series with the base of the RHET to make bistable states.
Abstract: The letter proposes a flip-flop circuit using a resonant-tunnelling hot electron transistor (RHET). The circuit uses a resistor in series with the base of the RHET to make bistable states. Preliminary tests have demonstrated that the circuit can be used as a static memory element, indicating that the RHET has a superior potential for use in memory and/or logic circuits.
27 citations
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21 Oct 2007TL;DR: This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD and shows that such nanoscale flip- flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days.
Abstract: Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation character ized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD. The theoretical distribution of transition times from one stable operation point to the other stable operation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days. Monte Carlo simulations are provided to validate the theoretical model and its predictions.
27 citations