Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.

An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop

Abstract: In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

Flip-flop circuit

Abstract: A clock control circuit is provided in a flip-flop circuit, since a first clock signal supplied to a master latch circuit is generated by an OR logic between a reference clock signal and a skew adjustment clock signal, a second clock signal supplied to a slave latch circuit is generated in accordance with the reference clock signal, the first clock signal has a phase advanced from the second clock signal by exactly an amount of a skew margin. An input signal is fetched into the flip-flop circuit at the rising edge of the first clock signal, then is output at the rising edge of the second clock signal. By this, malfunction due to the clock skew is prevented. The flip-flop circuit can operate as in the normal mode by holding the skew adjustment clock at a logic "0".

Optimization of scannable latches for low energy

Abstract: This paper covers a range of issues in the design of latches and flip-flops for low-power applications. First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. The data-switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of an energy-efficient family of configurations is introduced to make the comparison of different latch styles in the energy-performance space more fair. A recently proposed methodology for balancing hardware intensity in processor pipelines is applied to latch design to facilitate the selection of the objective function for tuning transistor sizes. The power dissipation of the clock distribution is taken into account, supported by simulations of extracted netlists for multibit datapath registers. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power level-sensitive scan mechanism is proposed, and results of a comparative study of scannable latches are shown. The applicability of the proposed scan mechanism to a wide variety of latches is demonstrated.

XNOR-based double-edge-triggered flip-flop for two-phase pipelines

Abstract: The conventional approach of double-edge-triggered flip-flops (DET-FFs) is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR-based approaches is difficult to reach the speed demand due to the delay of the XNOR -based clock generator. This paper proposes a new designed DET-FF based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25 um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.