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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


Papers
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01 Jan 2007
TL;DR: High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to complete the routing functionality of the AOLS node.
Abstract: The routing functionality by all-optically intercon- necting semiconductor-based all-optical logic gates and flip-flops is demonstrated in the frame of an all-optical label swapping (AOLS) network. We experimentally show that the output of the all-optical 2-bit correlator is capable of toggling the states of the integrated flip-flop every 2.5 ns via an adaptation stage. High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to com- plete the routing functionality of the AOLS node. The potential integration of these semiconductor optical amplifier integrated Mach-Zehnder interferometer-based devices make the proposed approach a very interesting solution for future packet switched optical networks. Index Terms—Address recognition, all-optical signal processing, Mach-Zehnder interferometer (MZI), optical flip-flop, optical label swapping, packet switching, semiconductor optical amplifier (SOA).

26 citations

Patent
21 Nov 1996
TL;DR: In this paper, a storage element having a data input terminal, a clock input terminal and a data output terminal is described, which is able to capture a logic value of a data signal on the input terminal with substantially zero setup time at an active edge of a clock signal.
Abstract: Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.

26 citations

Proceedings ArticleDOI
05 Oct 1998
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the sources of performance and power consumption bottlenecks in different design styles are revealed.
Abstract: In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance applications.

26 citations

Patent
12 Mar 2008
TL;DR: In this article, a method and apparatus for mapping flip-flop logic onto shift register logic is described, and a shift register is instantiated in a logical description of the circuit design for the chain of flips.
Abstract: Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design is identified. The chain of flip-flops includes first and second control signals. A shift register is instantiated in a logical description of the circuit design for the chain of flip-flops. A shift register is instantiated in the logical description for the chain of flip-flops. First and second control chains of flip-flops are instantiated in the logical description for the first and second control signals, respectively. A multiplexer is instantiated in the logical description and is configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains.

26 citations

Patent
Andy T. Nguyen1
12 Dec 2001
TL;DR: The flip-flops of as discussed by the authors can operate at very high clock rates, even at very low voltages, by passing high values to one node and low values to the other node of the latch.
Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

26 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868