Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Electrically Addressable Multistate Volatile Memory with Flip‐Flop and Flip‐Flap‐Flop Logic Circuits on a Solid Support

Abstract: Molecules that can perform complex mathematical operations are a potential alternative for transistor-type semiconductors. Since a molecular AND gate was demonstrated in 1993, logic gates, circuits, and even molecular memory elements have been reported. Most systems feature solution-based chemistry that inherently suffers from amassing chemical entities, thus compromising on operability and reversibility. Nevertheless, molecular information processing is becoming increasingly popular, since molecules are versatile synthetic building blocks for a bottom-up approach for information transfer and storage. In particular, the field of molecular logic has attracted much attention. 7] The behavior of molecules as logic gates that respond to specific inputs has found potential applications in sensors, medical diagnostics, molecular memory devices, and molecular computational identification (MCID) tags. To date, the applied logic is almost exclusively based on the underlying principle of mathematical operations performed on a system that can exist exclusively in two stable states, as introduced by George Boole. The ease of fabrication and wide variety of applications of binary systems has made them the status quo for (molecular) information processing technology. However, in order to cope with an ever-increasing information density, the viability of the binary numeral system also has to be considered. It is well-established that base three is the most efficient numeral system for transferring and storing information (see the Supporting Information). For instance, the information density in a ternary system is approximately 1.6 times higher than in a binary system. Therefore, exploration of molecular-based systems that are capable of existing in multiple states is highly desirable. The exploration of ternary memory devices is of particular interest, since it is expected that they eventually will replace the conventional flip-flop architecture in static random access memory (SRAM). Multivalue logic or multistate memory has rarely been demonstrated with molecular-based systems. 15] Herein we present a reconfigurable binary memory, and the first example of a ternary memory device constructed from a molecular-based assembly on a solid support. Fascinatingly, the assembly mimics both the well-known flip-flop logic circuit, commonly found in SRAM, and the even more interesting ternary flip-flap-flop logic circuit. The latter system enabled the storage of bits (binary digits) and trits (ternary digits) on a reconfigurable molecular-based assembly on a solid support. Furthermore, fourand five-state memory devices could be constructed for applications in dynamic random access memory (DRAM). The electrical addressability ensures chemical reversibility and stability, whereas the optical readout is fast and nondestructive. This result unequivocally demonstrates the proof-of-principle that the electrically addressable assemblies are capable of performing complex mathematical operations, and as such, brings us one step further towards the development of alternatives for transistor-type memory devices. The molecular memory was constructed from an assembly formed by alternating deposition of 1 and PdCl2 on indium tin oxide (ITO) coated glass functionalized with a pyridylgroup terminated monolayer (Scheme 1). Because the optical output is a precise function of the applied potential, the optical properties can be accurately controlled (Figure S1 in the Supporting Information). Therefore, multivalued information can be written on to the assembly by applying specific potential biases (vs. Ag/AgCl). The read–write cycle is completed by monitoring the metal-to-ligand charge-transfer (MLCT) band at l = 510 nm, which can be read out by a conventional UV/Vis spectrophotometer. Interestingly, the read–write operations are fundamentally different, that is, optical and electrochemical, respectively. The optical readout is nondestructive and allows for instantaneous data transfer.

Spin-MTJ based Non-volatile Flip-Flop

Abstract: Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.

A low-swing clock double-edge triggered flip-flop

Abstract: A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V/sub t/ transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

Radiation-induced clock jitter and race

Abstract: The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.

An Area and Power Efficient Radiation Hardened by Design Flip-Flop

Abstract: A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm2 /mg) at VDD=1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described