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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


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Proceedings ArticleDOI
23 May 2004
TL;DR: This paper presents a high-speed flip-flop-based frequency divider incorporating a new high- speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz.
Abstract: Frequency dividers play an important role in high speed communications systems. In particular, optical communication circuits demand frequency dividers capable of operating well above 10 GHz. This paper presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18 /spl mu/m CMOS process.

22 citations

Patent
12 Jul 1989
TL;DR: In this article, a tri-stable buffer is used in both the master and slave latches for asynchronous loading of replacement data into the flip-flop by using the tri-state condition.
Abstract: A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.

22 citations

Patent
Carl L. Shurboff1
17 Mar 1998
TL;DR: In this article, the phase detector circuit balances the amount of charge provided to a phase-locked loop near the in-phase condition to improve linearization of phase detector, and the AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps.
Abstract: A phase detector circuit includes a first flip flop, a second flip flop, a first charge pump and a second charge pump. Outputs of the flip flops directly enable the charge pumps in response to received clocking signals. A first delay circuit delays the output signal from the first flip flop to an AND gate which combines the delayed output signal and the output signal from the second flip flop. The AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps. The phase detector circuit balances the amount of charge provided to a phase locked loop near the in-phase condition to improve linearization of the phase detector.

22 citations

Patent
22 Dec 1999
TL;DR: In this article, the authors proposed a phase-frequency detector with anti-backlash pulses, which prevent the mapping of very short correction pulses occurring on the basis of small phase differences by use of an AND logic circuit controlling the RESET of two flip flop circuits.
Abstract: In a digital phase-frequency detector with anti-backlash pulses, which prevent the mapping of very short correction pulses occurring on the basis of small phase differences by use of an AND logic circuit controlling the RESET of two flip flop circuits, a waste time is shortened by reducing a duration of the RESET pulse. The integrable phase-frequency detector according to the invention can be used in fast digital phase-locked control loops, for example for tuners, frequency synthesizers in the field of mobile radio.

22 citations

Patent
17 Jun 1992
TL;DR: In this article, the output skew detection circuit detects common edge output skew across the n in phase output signals simultaneously and directly, and produces a threshold flag signal upon occurrence of a pulse signal having a pulse width greater than a specified pulse width threshold value corresponding to a maximum permitted output skew.
Abstract: An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n outputs. The output skew detection circuit senses common edge output skew across the n in phase output signals simultaneously and directly. A first logic gate has n inputs coupled to the n outputs, detects occurrence of either the first or last of the multiple common edge output signals, and generates a first skew detection edge signal at a first logic gate output. The first and last common edge output signals are the signals propagated with minimum and maximum propagation times tplhmin, tphlmin and tplhmax, tphlmax. A second logic gate has n inputs coupled to the n outputs in parallel with the first logic gate. The second logic gate detects occurrence of the other of the first and last of the multiple common edge output signals and generates a second skew detection edge signal at a second logic gate output. The respective inputs of a third logic gate are coupled to the first and second logic gate outputs. The third logic gate generates a pulse signal having a pulse width or pulse duration determined by the first and second skew detection edge signals at the inputs of the third logic gate for providing a pulse width measure of the maximum output skew tOSLH, tOSHL between the first and last of the multiple common edge output signals. A pulse width detection circuit such as a flip flop coupled to the third logic gate delivers a threshold flag signal upon occurrence of a pulse signal having a pulse width greater than a specified pulse width threshold value corresponding to a maximum permitted output skew.

22 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868