Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Flip-flop design

Abstract: A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30 . Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29 . Latch circuit 30 comprises an inverter 31 and a tristate NOR gate 32 . When the CLK (clock input signal) and CLRZ (the inverse of the clear input signal) are both low, the output of the tristate NOR gate 32 is forced low. Thus the input of inverter 31 is low so that the output signal, Q, is forced low and the inverse output signal, QZ, is forced high. When CLK is high and CLRZ is low the output of tristate NAND gate 29 is forced high so that the input to inverter 28 is high and the input to inverter 31 is low, thereby forcing Q low and QZ high. Thus the outputs Q and QZ are forced low and high respectively when CLRZ is low, regardless of the state of the CLK input.

Static/dynamic flip-flop

Abstract: A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively. In the illustrative embodiment, the second circuit is an arrangement which includes a first switching element with a first terminal connected to a first node, a control terminal responsive to the first intermediate complementary output signal and a third terminal for providing a third intermediate complementary output signal. The second circuit includes a second switching element having a first terminal connected to the first node, a control terminal responsive to a second complementary input signal and a third terminal for providing a fourth intermediate complementary output signal. The second circuit further includes a third switching element having a first terminal connected to the first node, a second terminal connected to a source of supply and a control terminal connected to a source of a clock signal.

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

Abstract: The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

Abstract: Positron emission tomography (PET) is a nuclear functional imaging technique that produces a three-dimensional image of functional organs in the body. PET requires high resolution, fast and low power multichannel analog to digital converter (ADC). A typical multichannel ADC for PET scanner architecture consists of several blocks. Most of the blocks can be designed by using fast, low power D flip-flops. A preset-able true single phase clocked (TSPC) D flip-flop shows numerous glitches (noise) at the output due to unnecessary toggling at the intermediate nodes. Preset-able modified TSPC (MTSPC) D flip-flop have been proposed as an alternative solution to alleviate this problem. However, the MTSPC D flip-flop requires one extra PMOS to suspend toggling of the intermediate nodes. In this work, we designed a 7-bit preset-able gray code counter by using the proposed D flip-flop. This work involves UMC 180 nm CMOS technology for preset-able 7-bit gray code counter where we achieved 1 GHz maximum operation frequency with most significant bit (MSB) delay 0.96 ns, power consumption 244.2 μW (micro watt) and power delay product (PDP) 0.23 pJ (Pico joule) from 1.8 V power supply.

A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications

Abstract: A new fast low-power flip-flop, called pulse-triggered TSPC flip-flop (PTTFF), is proposed. PTTFF uses a conventional latch structure clocked by a short pulse train, and it indeed acts as a flip-flop. The new flip-flop uses only 5 MOS transistors with only one transistor being clocked. Both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption of the flip-flop itself and the clocking system. For a pipelined FIR macro, utilizing the proposed PTTFF can save up to 63% of power consumption of the clocking system. PTTFF can also operate very fast. The maximum toggle rate of PTTFF can be as high as 3 GHz if designed in a 0.6 /spl mu/m CMOS technology.