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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


Papers
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Patent
12 Dec 2006
TL;DR: In this paper, a latch circuit and a flip-flop circuit are proposed to suppress the occurrence of a single-event effect and eliminate adverse effects thereof on the circuit, respectively.
Abstract: Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

20 citations

Journal ArticleDOI
TL;DR: Electrical characteristics remain identical after repeated measurements after a model matching the presented circuits' behavior was carried out, permitting the design of more complex circuits.
Abstract: This paper presents organic based logic and memory circuits. All those circuits are made with organic N- and P-type transistors. Organic complementary NAND and NOR gates were characterized and show performance equivalent to or better than the literature-reported ones. The presented memory circuits include an SRAM memory point and an edge-triggered flip-flop. The flip-flop is made of six organic two-input and three-input NAND gates, representing a total of 26 organic transistors for a surface of 170 mm2. The maximum operating frequency of this flip-flop is 220 Hz under a supply of ±20 V. All the circuits were manufactured using a standard organic sheet-to-sheet process in ambient air. Electrical characteristics remain identical after repeated measurements. Finally, a model matching the presented circuits' behavior was carried out, permitting the design of more complex circuits.

20 citations

Patent
13 Nov 1978
TL;DR: In this article, a plurality of master latches whose outputs are selectively connected to a single-slave latch is provided. But the outputs of the slave latch may be discretionarily connected to particular master latch inputs depending upon the specific circuit arrangement desired.
Abstract: Apparatus is provided comprising a plurality of master latches whose outputs are selectively connected to a single-slave latch. The outputs of the slave latch may be discretionarily connected to particular master latch inputs depending upon the specific circuit arrangement desired. Both the master latches and the slave latch may incorporate implicit input gating which implement particular logic functions.

20 citations

Patent
20 Dec 2002
TL;DR: In this paper, a scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output, coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed.
Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.

20 citations

Patent
26 Nov 2002
TL;DR: In this article, the first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch, and the second latch includes an isolation switch with a reset signal.
Abstract: A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868