Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

All-optical flip-flop operations in a coupled element bistable device

Abstract: An optical bistable device composed of coupled nonlinear elements is proposed. This device features optical bistability without hysteresis. It is shown theoretically that a set-reset type (S-R) flip-flop operation can be easily achieved on an all-optical basis by utilising nonhysteretic bistable characteristics.

Scan flip flop, semiconductor device, and production method of semiconductor device

Abstract: There is provided a flip flop circuit with a scan structure which is formed by an input section of a dynamic circuit and an output section of a static circuit wherein data is taken in within an interval of a short pulse width as compared with a clock cycle. In the dynamic circuit of the input section, the number of serially-connected MOS transistors to which a data signal is input is smaller than the number of serially-connected MOS transistors to which a test input signal is input. With this structure, the speed of operation is increased at the time of data storage for a data signal input, and the number of MOS transistors is reduced.

Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard an n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.

A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's

Abstract: We report master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBT's. The fabricated HBT's had an f/sub T/ of 107 GHz and an f/sub max/ of 110 GHz. To maximize the speed, the logic swing and transistor size in the IC were optimized. In the D-FF, to facilitate the high-speed testing, a selector circuit was integrated on the same chip. As a result, the operation of this IC was confirmed up to 40 GHz, which is the highest speed in D-FF. >

Flip flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption by reducing the frequencies of a clock signal in a circuit in which timing adjustment is relatively simple while suppressing the increase of a circuit area by reducing the number of elements. SOLUTION: A latch circuit 1 fetches an input signal FD when a clock signal CLK is in an H state. A latch circuit 2 fetches the input signal FD when the clock signal CLK is in an L state. A multiplexer 3 selects an output signal Q of the latch circuit 1 when the clock signal CLK is in the L state, or selects the output signal Q of the latch circuit 2 when the clock signal CLK is in the H state, and outputs it. Thus, it is possible to fetch the input signal in both the rising and falling states of the clock signal. Consequently, the frequencies of the clock signal can be reduced into half, and power consumption can be reduced by reducing the frequencies of the clock signal.