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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


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Patent
01 Apr 1992
TL;DR: In this paper, a BICMOS passgate circuit (PSGT3) is coupled to a bipolar output circuit (Q1,Q3) for transient charging and discharging of load capacitance (C L ) at the pass-gate output (V OUT ).
Abstract: A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V OUT ) for transient charging and discharging of load capacitance (C L ) at the passgate output (V OUT ) The bipolar output circuit provides increased sinking and sourcing output drive current and s amplification of sinking and sourcing drive current at the passgate output V OUT in response to data signals at the passgate input (V′ IN ) in the transparent operating mode An MOS input logic circuit coupled to the passgate input (V′ IN ) includes clock signal inputs ( CP ¯ , CP ¯ ) for implementing transparent and blocking operating modes The MOS input logic circuit (QP3,QP4,QP5,QP6,NAND1) is coupled to the bipolar output circuit (Q1,Q3) and is constructed to control the conducting states of the bipolar pullup (Q1) and pulldown (Q3) transistor elements for transient turn on of one of the respective bipolar pullup and pulldown transistor elements during respective switching transitions at the passgate output (V OUT ) The MOS input logic circuit is also connstructed for turn off of the bipolar pullup (Q1) and pulldown (Q3) transistor elements follow switching transitions at the output (V OUT ) and during the blocking operating mode A final latchback circuit (LTBK2) (INV3,INV4) is coupled to the passgate output to latch an output data signal and for pulling up the final output (V OUT ) to a high potential level power rail (V CC )

20 citations

Journal ArticleDOI
TL;DR: In this paper, a low-power sense-amplifier-based flip-flop (FF) is presented, using a simplified single-ended pass transistor-based latch design.
Abstract: A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post-layout simulations.

20 citations

Patent
04 Sep 1997
TL;DR: In this article, a power controller device using a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load is presented.
Abstract: A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

20 citations

Journal ArticleDOI
TL;DR: In this paper, some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems are proposed that can recover from soft errors caused by cosmic rays and particle strikes by utilizing local redundancy and inner feedback techniques.
Abstract: In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.

20 citations

Patent
31 May 2000
TL;DR: The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave circuit relative to the sample-tohold transition of a master circuit as mentioned in this paper.
Abstract: An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868