Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
Papers published on a yearly basis
Papers
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TL;DR: A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops and shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal <0.65.
Abstract: A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be as high as 86% when the input is idle.
20 citations
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05 May 2005TL;DR: In this paper, the scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.
Abstract: A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.
19 citations
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26 May 1982TL;DR: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters as discussed by the authors, which allows data to enter the latch when the latch is disabled.
Abstract: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.
19 citations
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07 Dec 1979
TL;DR: In this paper, a flip-flop circuit capable of high speed and of low power consumption is presented, which has a master flipflop including a logic gate circuit, and a slave flip flop circuit also including an output logic circuit.
Abstract: Disclosed is a flip-flop circuit capable of high speed and of low power consumption which has a master flip-flop including a logic gate circuit, and a slave flip-flop circuit also including a logic gate circuit, and a means for supplying a preset signal or a clear signal to the logic gate circuit of the slave flip-flop circuit or to an output logic circuit. Specifically, a binary type flip-flop circuit with preset/clear functions suitable for a ring counter and a ripple counter, and assembled by means of integrated circuit technology, is disclosed.
19 citations
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IBM1
TL;DR: In this article, a boundary scan cell includes a shift latch, an update latch, and a flushable latch that each have at least a respective data input and at least data output.
Abstract: A boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.
19 citations