Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories

Abstract: In one example, a generally conventional flip-flop circuit is used, including a pair of input field-effect transistors having their gates connected respectively to a pair of circuit nodes A and B. During a preset portion of the cycle, both nodes A and B are preset to an initial reference potential V R , set so that the transistors turn partially ON and act as variable resistors. Thereafter, an unknown voltage V X to be sensed is connected to node A, V X being equal to V R ± ΔV. The flip flop then responds to differential conductivity between the transistors, to produce a binary output voltage at one of two levels set by the sense of ΔV, plus or minus. In a semiconductor RAM circuit, selected memory cell capacitors are connected in sequence to node A, and the flip-flop circuit senses the cell charge and produces an amplified output representative thereof, which is later fed back to the memory cell to refresh the charge originally stored therein.

Sense circuit employing complementary field effect transistors

Abstract: A sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with inputs connected to first and second I/O nodes, respectively, and with outputs capable of being clamped to one or the other of the two supply lines powering the inverters. Selectively and sequentially enabled cross-coupling transmission gates are connected between the output of each inverter and the input to the other inverter, and selectively enabled biasing transmission gates are connected between the input and output of each inverter. In the operation of the circuit, the two input nodes are first precharged to a predetermined value by enabling the biasing gates. A signal is then applied to one I/O node causing its potential to vary from its quiescent value. Then, the cross-coupling gate connected to the output of the inverter whose input is connected to the one I/O node is first enabled and, subsequently, the other cross-coupling gate is enabled. When the two cross-coupling gates are enabled, the inverters are latched and form a flip flop with the first I/O node clamped to the supply line having the same binary signal and the second I/O node clamped to the other power supply line.

Device for programmable frequency divider

Abstract: The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.

Compact Organic Complementary D-Type Flip-Flop Circuits Fabricated with Inkjet Printing

Abstract: Organic thin-film transistors (OTFTs) have received significant consideration in recent years for potential deployment in low-cost and large-area printed electronics. D-type flip-flop (D-FF) circuits are one of the most important logic gates for data processing and storage in such applications. Previous work has reported on NAND-based organic D-FF circuits. Although the demonstrated printed circuits exhibit low voltage operation at 10 V, each D-FF circuit requires 34 TFT devices and occupies an area of 192 mm2 per D-FF circuit. This paper demonstrates inkjet-printed organic D-FF circuits with a compact circuit design using clocked inverters and transmission gates and compares the occupied area and the circuit performance with those of NAND-based organic D-FF circuits. The compact organic D-FF circuits require only 18 OTFT devices, and can use 60% less area than NAND-based organic D-FF circuits fabricated by the same process. In addition, the compact organic D-FF circuits exhibit a shorter propagation delay time than the NAND-based D-FF circuits. The mechanism for the shortened delay time will be discussed in detail, based on SPICE simulations. These results demonstrate the high potential of these compact organic D-FF circuits in printable electronics.

Low power scan flip-flop cell

Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.