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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


Papers
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Journal ArticleDOI
20 Sep 2004
TL;DR: The process technologies and fabrication methodologies for digital superconductor integrated circuits are described and the key developments required for the next generation of 100-GHz logic circuits are discussed.
Abstract: Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.

78 citations

Journal ArticleDOI
TL;DR: The photochromic fluorescence switching of a fulgimide derivative was used to implement the first molecule-based D (delay) flip-flop device, which works based on the principles of sequential logic.
Abstract: The photochromic fluorescence switching of a fulgimide derivative was used to implement the first molecule-based D (delay) flip-flop device, which works based on the principles of sequential logic. The device operates exclusively with photonic signals and can be conveniently switched in repeated cycles.

75 citations

Proceedings ArticleDOI
01 Aug 2006
TL;DR: This paper proposes a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.
Abstract: Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.

75 citations

Patent
Mel Bazes1
26 Mar 1990
TL;DR: An integrated circuit for recovering the clock and data information from phase-encoded serial data is presented in this paper, which includes a synchronous delay line coupled to a waveform digitizer and a wave-form synthesizer.
Abstract: An integrated circuit for recovering the clock and data information from phase-encoded serial data The circuit includes a synchronous delay line coupled to a waveform digitizer and a waveform synthesizer The waveform digitizer receives and converts the phase-encoded data into a string of bits whose value represent the logic levels of an encoded data at T p /N intervals where T p is the reference clock period and N is the resolution of the waveform digitizer The encoded data may be one of several phase-encoded serial data such as Manchester coding The digitized output from the waveform digitizer is input to a transition detector, where the locations of the transitions (bit-boundary transitions and bit-center transitions) of the digitized encoded data are extracted An AND stage comprising N AND gates is coupled to the waveform digitizer and the waveform synthesizer for masking out the bit-boundary transitions and passes the bit-center transitions The output from the AND stage (a binary word) is coupled to a pair of encoders The encoders are coupled to an adder and an L-type register which are used for compensating for missing bit-center transitions or for the presence of two bit-center transitions A digital filter coupled to the L-type register allows the present invention to achieve lockon immediately and to filter out phase jitter The digital filter is further coupled to a shifter in the waveform synthesizer for synthesizing the clock information of the encoded data on one hand, and for providing mask bits to the AND stage on the other hand The clock information of the encoded data is synthesized by the shifter in the waveform synthesizer over a digital-to-time domain converter in the waveform synthesizer Finally, the data information of the phase-encoded serial data is regenerated by a D-type flip flop which receives encoded data over a delayed stage from its D input and also receives the clock information over its clock input

74 citations

Patent
19 Dec 1989
TL;DR: In this paper, a synchronous latch device macrocell is presented, which includes an input gate section and a scannable latch section, which are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits.
Abstract: A synchronous latch device macrocell which includes an input gate section and a scannable latch section. Both sections are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits. The non-inverting output of the latch section connects to an output pin and provides a signal representation of the state of the latch device. The output pin is externally connected through a conductor wire to either one of a pair of complementary data input pins of the input gate section. The connection made is selected as a function of which data input pin connection provides the faster loading of the latch device as viewed from the source of the signal applied to the load control pin of the input gate section.

72 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868