Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Bistable flip-flop with reset control

Abstract: A bistable flip-flop with reset control is provided. The flip-flop includes a storage cell having a first inverter whose input can receive a write signal from an input signal delivered to the input terminal of the first inverter, and a second inverter which is feedback-mounted with respect to the first inverter. The flip-flop also includes a first switch controlled by a reset signal for enforcing a specified logic state at the input of the first inverter when the reset signal is active, and a second switch controlled by the reset signal so as to prevent the first inverter from receiving a write signal in a logic state opposite to the specified state when the reset signal is active.

Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization

Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

Method and system for disabling a scanout line of a register flip-flop

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop. The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation. When the scan output is disabled from following the data output, the scan output is driven to a predetermined logic value.

Low power radio frequency divider

Abstract: In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.

Low-power/high-performance explicit-pulsed flip-flop using static latch and dynamic pulse generator

Abstract: Latches and flip-flops play important roles in the building of digital CMOS circuits. In the paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic pulse generator are proposed. The pulse generator is then used with the proposed latch to create a low-power and high-performance single edge-triggered flip-flop (SETFF). The proposed positive level-sensitive latch deploys two non-precharge (static) n-stages (SN) in a true-single-phase-clocking (TSPC) scheme. We therefore named our latch SN2. This is because the TSPC latches have the advantage of single clock distribution, less clock routing area, high-speed and no clock skew. Based on the 0.18-μm single-poly six-metal CMOS technology, the SPECTRE simulation results derived for typical input activities showed that the latch can attain a maximum power saving of 29.1% when compared to other reported designs. As for our proposed flip-flop that is derived from the proposed SN2 latch with incorporation of a dynamic pulse generator circuit, it is able to outperform other reported works by about 16.2% to 67.4% for its power-delay product (PDPCQ) that is taken with respect to the clock-to-output delay. The two new designs are therefore suitable for used in low-power and high-performance CMOS VLSI/ULSI applications.