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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


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Patent
08 May 2013
TL;DR: A flip-flop circuit may include a first latch and a second latch as discussed by the authors, which are clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.
Abstract: A flip-flop circuit may include a first latchand a second latch. The first latch, which may operate as a "master" latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a "slave" latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

15 citations

Proceedings ArticleDOI
T. Uemura1, T. Baba1
01 May 2001
TL;DR: A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated.
Abstract: A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTT's latching function and the MOSFET's switching function, the number of devices required for the D-FF circuit was greatly reduced to two from the thirty required for the FET-only circuit.

15 citations

Proceedings ArticleDOI
19 Apr 1993
TL;DR: This paper provides an analysis of flip-flop testability with respect to resistive bridging faults with problems inherent to their detection not encountered in combinational circuits.
Abstract: This paper provides an analysis of flip-flop testability with respect to resistive bridging faults. Problems inherent to their detection not encountered in combinational circuits are discussed, and practical solutions are proposed to overcome the main difficulties. >

15 citations

Patent
28 Jun 1957

15 citations

Patent
05 Dec 1986
TL;DR: In this article, a flip-flop circuit is provided for use in a phase-locked loop circuit, the flip flop having two signal paths for selecting a VCO output during velocity lock and phase lock.
Abstract: A flip-flop circuit is provided for use in a phase-locked loop circuit, the flip-flop having two signal paths for selecting a VCO output during velocity lock and phase lock. The two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock. The circuit is also useful in any application where a clock to output delay of a flip-flop connected for normal operation, must have its propagation delay matched to a circuit which simply delays a signal by the same amount.

15 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868