Topic
Flip-flop
About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.
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06 Oct 2010
TL;DR: An on-die monitoring scheme to detect and count transient faults resulting, as well as not resulting in output SEs, affecting the inputs of data-path latches/flip-flops, thus discovering intrinsic weaknesses of design or process.
Abstract: In this paper we propose an on-die monitoring scheme to detect and count transient faults (TFs) resulting, as well as not resulting in output SEs, affecting the inputs of data-path latches/flip-flops. This approach allows an early monitoring of the latches/flip-flops vulnerability to TFs, thus discovering intrinsic weaknesses of design or process. The proposed monitoring scheme features a very low impact on area overhead and power consumption, thus being suitable to be deployed within any IC.
14 citations
TL;DR: In this article, the design of 3-valued R-S & D type of flip-flops is described and a new clock is developed according to which circuit makes transition as well as retains present, past and former past information.
Abstract: Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appears to have lesser power consumption and better speed of operation.
14 citations
TL;DR: In this paper, a novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs) was proposed to enhance the hardness of the single event upset.
Abstract: The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).,To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.,To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.,The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.
14 citations
24 May 2015
TL;DR: Novel pulse-clocked latch based flip-flops that mitigate not just single event upsets but also single event transients that are an increasing threat in high performance logic.
Abstract: Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.
14 citations
Patent•
30 Jun 1988TL;DR: In this article, an STL flip flop circuit composed of a pair of latch circuits, the first latch circuit receiving R and S inputs and the clock signal and floating relative to the other latch circuit, is referenced to ground and is driven by the output of the floating latch circuit.
Abstract: The disclosure relates to an STL flip flop circuit composed of a pair of latch circuits, the first latch circuit receiving R and S inputs and the clock signal and floating relative to the other latch circuit. The second latch circuit is referenced to ground and is driven by the output of the floating latch circuit. All components are of the schottky type, the semiconductor devices being schottky clamp transistors and the diodes being either TiW or PtSi type. In accordance with a second embodiment of the invention, a pair of inverter circuits are each coupled to the R and S inputs of the first embodiment, one of the inverters being controlled by an external data source, whereby, the inverters always each provide opposite outputs to the R and S inputs, depending upon the data input. Schottky clamp transistors and two different types of schottky diodes are utilized.
14 citations