Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Abstract: A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL' soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEL soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insnlator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable.

A high performance D-flip flop design with low power clocking system using MTCMOS technique

Abstract: Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in International technology roadmap for semiconductors. In any integrated circuit, clock distribution network and flip -flop consumes large amount of power as they make maximum number of internal transitions. In this paper, various techniques for implementing flip-flops with low power clocking system are analyzed. Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered flip-flop (DEFF). We propose a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF. In addition, to build a clocking system, double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.

Method and apparatus for a scannable hybrid flip flop

Abstract: A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.

Improving path delay testability of sequential circuits

Abstract: We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible.

Flip-flop having gated inverter feedback structure with embedded preset/clear logic

Abstract: A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.