Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

2-level series-gated current mode logic with inductive components for high-speed circuits

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique

Abstract: Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in International technology roadmap for semiconductors. In any integrated circuit, clock distribution network and flip -flop consumes large amount of power as they make maximum number of internal transitions. In this paper, various techniques for implementing flip–flops with low power clocking system are analyzed. Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered flip-flop(DEFF). We propose a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF. In addition, to build a clocking system, double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.

Oscillation circuit of microcomputer

Abstract: PURPOSE:To reduce electromagnetic-wave disturbances to peripheral equipment from an oscillation circuit used in a microcomputer, by dispersing the spectrum distribution of the higher harmonic component of the electromagnetic waves. CONSTITUTION:Delay circuits 121-125 which are selected by means of switches SW1-SW5 are provided and the selection is made in accordance with outputs of shift registers 13. Then the output of the delay circuits is inputted to a control section 10 after they are combined to an output f1 whose frequency fluctuates in the vicinity of f0 by an OR gate G1. The delaying times TD1-TD5 of the delay circuits 121-125 are set at random and the set delaying times Td1-TD5 are successively selected by the parallel outputs of the shift registers 13 which clock (CK) the f0. However, the shift registers 13 are cleared when read/write signals R/W from the microcomputer controlling section 10 become the write mode and all the outputs SW1-SW4 of flip flops FF1-FF4 of each stage are made zero. As a result, the output of an OR gate G2 and inverter I respectively become '0' and '1' and the flip flop FF1 of the 1st stage is set to '1'.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To operate a flip-flop circuit at high speed which is the important component of a semiconductor integrated circuit and to reduce the space required. SOLUTION: A first latch circuit 1 for fetching data is of dynamic type, a second latch circuit 2 for storing, holding and outputting the data is of a static type. Both circuits 1 and 2 are connected serially and connected through a buffer circuit 14 to an output terminal Q. A switch control circuit 15 receiving a clock CK complementarily operates a first switch circuit 11 and a second switch circuit 12. A capacitor Cm parasitic to a node A holds a signal D only in the OFF period of a switch 11, shifts it to a second storage circuit 13 at the fall of the CK and statically holds it. The second storage circuit 13 is composed of an inverter and a clocked inverter for instance and constitutes a positive feedback loop by control from the switch control circuit 15.

Optical delay type flipflop and shift register using it

Abstract: An optical D flipflop comprising a 2×1 optical switch and a optical bistable element. The flipflop has a first input end adapted to receive optical digital data, a second input end adapted to receive a biasing optical signal and at least one output end for emitting a light beam comprising the bias signal or optical information pulses, depending upon the state of a clock signal applied to the signal flip flop switch. The flip flops, when connected in cascade through light branching circuits, act as a shift register.