Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Scannable flip-flop with non-volatile storage element and method

Abstract: A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers

Abstract: This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.

Analysis of harmonic contents of switching waveforms emitted by the ultra high speed digital CMOS integrated circuits for use in future micro/nano systems applications

Abstract: In this paper we outline the influence of transistor model quality and input signal on the estimates of higher order harmonic contents of switching waveforms emitted by the high performance and low power digital integrated circuits. Accurate estimates of higher order harmonic contents are essential in the design and development of highly integrated wireless communication systems. Harmonic contents are used to design tapered buffer chains, but the design quality is influenced by the device model discontinuities. We used Cadence Spectre and Matlab to analyze the spectrum of different flip flop and latch structures. They showed steep spectrum roll-off after the knee frequency. As a concrete example, various kinds of latches and flip-flops, which have the fastest switching capability, are evaluated by using BIM3v3 and BSIM4 transistor models.

Mos master-slave flip-flop with reduced number of pass gates

Abstract: A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances IDDQ- testability with respect to known flip-flops.

Resettable binary flip-flop of the semiconductor type

Abstract: A bistable flip-flop circuit utilizing insulated gate field effect transistors in a plurality of AND, NOR and inverter circuits connected to receive a signal and the inverse thereof on two inputs and to supply an output signal and the inverse thereof on two outputs, the outputs being resettable to specific levels upon the application of a reset signal to a reset input.