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Frequency divider

About: Frequency divider is a(n) research topic. Over the lifetime, 16884 publication(s) have been published within this topic receiving 116119 citation(s).

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Papers
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Journal ArticleDOI: 10.1109/4.229400
Abstract: A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

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Topics: Delta modulation (63%), Delta-sigma modulation (62%), PLL multibit (61%) ...read more

588 Citations


Journal ArticleDOI: 10.1109/4.643663
Abstract: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

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Topics: Direct digital synthesizer (64%), Frequency synthesizer (60%), Frequency divider (57%) ...read more

432 Citations


Journal ArticleDOI: 10.1109/4.766815
H.R. Rategh1, Thomas H. Lee1Institutions (1)
Abstract: Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW.

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Topics: Frequency divider (60%)

423 Citations


Journal ArticleDOI: 10.1109/4.848214
Cicero S. Vaucher1, I. Ferencic2, M. Locher2, S. Sedvallson2  +2 moreInstitutions (2)
Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

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Topics: Current divider (73%), Frequency divider (72%), Wilkinson power divider (68%) ...read more

382 Citations


Journal ArticleDOI: 10.1109/4.318
Abstract: A general theory that allows the accurate linear and nonlinear analysis of any crystal oscillator circuit is presented. It is based on the high Q of the resonator and on a very few nonlimiting assumptions. The special case of the three-point oscillator, that includes Peirce and one-pin circuits, is analyzed in more detail. A clear insight into the linear behavior, including the effect of losses, is obtained by means of the circular locus of the circuit impedance. A basic condition for oscillation and simple analytic expressions are derived in the lossless case for frequency pulling, critical transconductance, and start-up time constant. The effects of nonlinearities on amplitude and on frequency stability are analyzed. As an application, a 2-MHz CMOS oscillator which uses amplitude stabilization to minimize power consumption and to eliminate the effects of nonlinearities on frequency is described. The chip, implemented in a 3- mu m p-well low-voltage process, includes a three-stage frequency divider and consumes 0.9 mu A at 1.5 V. The measured frequency stability is 0.05 p.p.m./V in the range 1.1-5 V of supply voltage. Temperature effect on the circuit itself is less than 0.1 p.p.m. from -10 to +60 degrees C. >

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Topics: Vackář oscillator (68%), Frequency drift (65%), Voltage-controlled oscillator (64%) ...read more

372 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021113
2020239
2019331
2018342
2017395

Top Attributes

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Topic's top 5 most impactful authors

Sheng-Lyang Jang

93 papers, 631 citations

Herbert Knapp

35 papers, 496 citations

Klaus Aufinger

34 papers, 718 citations

Sheng-Lyang Jang

32 papers, 451 citations

Kiat Seng Yeo

27 papers, 267 citations

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