Frequency drift

About: Frequency drift is a research topic. Over the lifetime, 5054 publications have been published within this topic receiving 56191 citations. The topic is also known as: chirp rate.

A $\pm$ 0.5% Precision On-Chip Frequency Reference With Programmable Switch Array for Crystal-Less Applications

Abstract: An on-chip frequency reference is designed for low-power, low-cost, and fully integrated system-on-chip designs. In this relaxation oscillator, pseudodifferential architecture is used to eliminate frequency variation caused by bias current, and interleaving capacitors are implemented to extend its discharge time. A low-leakage programmable switch array (PSA) trimming method is proposed to calibrate the first- and second-order temperature coefficients (TCs) of the composite resistor. The oscillator was fabricated in a 0.35-μm 2P4M CMOS process with an area of 0.162 mm2. The oscillator operates at 130 kHz, and measurement results show that it achieves a frequency variation of less than ±0.5% over a temperature range of -20 °C-100°C and less than ±0.4% over a supply voltage range of 1-3 V.

Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies

Abstract: An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.

A Local Oscillator for Chip-Scale Atomic Clocks at NIST

Abstract: We describe the first local oscillator (LO) that demonstrates viability in terms of performance, size, and power, for chip-scale atomic clocks (CSAC) and has been integrated with the physics package at the National Institute of Standards and Technology (NIST) in Boulder, CO. This voltage-controlled oscillator (VCO) achieves the lowest combined size, DC power consumption, phase noise, and thermal frequency drift among those previously reported, while achieving a tuning range large enough to compensate for part tolerances but small enough to permit precision locking to an atomic resonance. We discuss the design of the LO and the integration with the NIST physics package.

Filter stabilized single oscillator transceivers

Abstract: A transceiver, adapted for use as either a master or a slave in a duplex pair, has a single, voltage-tunable, solid-state oscillator to provide the carrier frequency wave, a small portion of which is mixed with the received wave and applied therewith to a single ended mixer; an automatic gain-controlled loop cancels transmitter input modulation from the receiver output. The desired oscillator carrier frequency of the master transceiver is locked to a frequency within the pass band of an RF filter at the receiver input and separated from the center frequency of the filter by one-half the receiver IF frequency. The slave transceiver is first locked to a frequency within the pass band of the filter on the opposite side of its center frequency and separated therefrom by one-half the IF frequency (the slave thus offset from the master by their common IF frequency). Thereafter, upon sensing output from its IF amplifier (from the master), the slave is switched to operate in response to AFC developed by the received signal, such that the master and slave transceivers are locked together at frequencies differing by their common IF frequency. The RF filter also limits the signals to which the receiver can respond. An integrating amplifier provides demodulator and AFC filtering and, together with a bistable device, initial sweeping of the oscillator control voltage in respective directions depending on being in the master mode or the slave mode. Internal auxiliary modulation provides for pre-transmission transmitter modulation cancellation and frequency stability.

A 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach

Abstract: In this paper, we propose a high frequency, fully integrated frequency-locked loop (FLL) design based on a new architecture of a CMOS frequency-to-voltage converter. The design is similar to a phase-locked loop (PLL) in the way that it generates an output signal that tracks an input reference signal, however, in this case the two signals are synchronized in frequency and not in phase. The frequency of the FLL output could be also controlled by an input voltage, therefore, it could be also used as an integrated high-precision voltage-controlled oscillator. The proposed FLL is very fast, operates over a wide frequency range and occupies a small integrated area compared to an equivalent PLL.