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Showing papers on "Gate count published in 1991"


Proceedings ArticleDOI
26 Jun 1991
TL;DR: The design of a fast multiplier implemented using either or both of the following techniques is illustrated.
Abstract: Multiplication represents one of the major bottlenecks in most digital processing systems Depending on the wordsize, several partial products are added to evaluate the product The well-known shift-and-add algorithm uses minimal hardware but has unacceptable performance for most applications Several parallel fast multiplication schemes have been suggested using several levels of blocks containing full adders This paper presents the design of a fast multiplier implemented using either (7,3) parallel counter or (7:3) compressor circuits for implementation in CMOS technology, The resulting 16 by 16-bit multiplier has less delay than conventional fast multipliers, although the gate count is about 10% higher

88 citations


Patent
31 Jan 1991
TL;DR: In this paper, a binary adder of the carry multiplex signal selection type is presented, where multiple levels of multiplexing between parallel carry paths are used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria.
Abstract: A binary adder of the carry multiplex signal selection type wherein multiple levels of multiplexing between parallel carry paths is used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria. The resulting adder employs a plurality of different adder stages of successively increasing complexity and achieves performance time that can be characterized as being of the order of Log2 (n), wherein n represents bit count, and as requiring a gate count that is of the order of n. Both internal arrangement of the adder stages and interconnection arrangements therefor are disclosed.

7 citations


Journal ArticleDOI
TL;DR: The design of an efficient, robustly testable CMOS totally self-checking (TSC) checker for k-out-of-2k codes is treated and a new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented, which retains its properties under the stuck-open fault model.
Abstract: The design of an efficient, robustly testable CMOS totally self-checking (TSC) checker for k-out-of-2k codes is treated. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers especially under the stuck-open fault model, owing to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented, which retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (>70%) in gate count, gate inputs and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed implementation is better than Kundu's in all respects for k-out-of-2k codes.

3 citations


Journal ArticleDOI
TL;DR: In this article, a high speed 1:4 demultiplexer IC architecture featuring output bit alignment, reduced gate count, and improved timing over a conventional tree-type architecture is presented.
Abstract: A high speed 1:4 demultiplexer IC architecture featuring output bit alignment, reduced gate count, and improved timing over a conventional tree-type architecture demultiplexer is presented. Simulation results at 20 Gbit/s are obtained using an HBT process. The architecture can be directly extended to higher order demultiplexers, and is applicable to other processes supporting current-mode logic.

2 citations


Book ChapterDOI
M. Bartel1
25 Sep 1991
TL;DR: This paper presents a technique for designing fault tolerant combinational circuits by means of linear error correcting codes (ECC) to increase the reliablity R(t) and compares it with the Triple Modular Redundancy (TMR) technique which uses a restoring organ with a minimal gate count and is therefore a stiff competitor.
Abstract: This paper presents a technique for designing fault tolerant combinational circuits (Fig. 1c) which are functional blocks of a VLSI-system, by means of linear error correcting codes (ECC) to increase the reliablity R(t). This new technique, called CLC (coded logical channels), is a concurrent error detection and correction approach. At first this paper presents the technique for single-output circuits and then it extends this technique to multi-output circuits and compares it with the Triple Modular Redundancy (TMR) technique which uses a restoring organ with a minimal gate count and is therefore a stiff competitor.

1 citations


Proceedings ArticleDOI
S. Lai1, M. Wang1
23 Sep 1991
TL;DR: To provide BiCMOS gates throughout an array without disrupting the majority CMOS logic, a Bi CMOS base cell was pitch-matched to the existing CMOS channelless array and distributed uniformly in the core.
Abstract: To provide BiCMOS gates throughout an array without disrupting the majority CMOS logic, a BiCMOS base cell was pitch-matched to the existing CMOS channelless array and distributed uniformly in the core. This architecture maintains usable gate count when the BiCMOS capability is introduced and allows reuse of the existing CMOS macrocells. >