Showing papers on "Gate count published in 1992"

All-node switch-an unclocked, unbuffered, asynchronous switching apparatus

Abstract: Disclosed is an apparatus for switching input port connections to output port connections quickly and dynamically using a new asynchronous approach to resolve contention. The disclosed ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is completely completely void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays - on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

VLSI module for high-performance multiply, square root and divide

Abstract: A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and ean be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 mu m CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected. >

Single chip pulse-width modulator based on a compressed look-up table

Abstract: Reference waveforms for three-phase pulse-width modulation (PWM) circuits are normally retained in ROM The authors describe a novel technique based on the second forward difference for compressing the reference information into a simple logic circuit A complete PWM circuit containing two look-up tables is implemented in a single-chip programmable device A significant reduction in gate count results with a semicustom implementation A novel Fourier-based simulation technique which can detect the nonharmonic spectral components generated by asynchronous PWM is described The technique offers a simpler solution than complex analytical methods based on double Fourier integration and fast Fourier analysis Simulated results, with an accuracy of -75 dB, compared favorably with the practical results obtained from the single-chip circuit >

Minimum-complexity optical architecture for look-up table computation in the residue number system

Abstract: An optical outer product architecture is presented which performs residue arithmetic operations via position-coded look-up tables. The architecture can implement arbitrary integer- valued functions of two independent variables in a single gate delay. The outer product configuration possesses spatial complexity (gate count) which grows linearly with the size of the modulus, and therefore with the system dynamic range, in contrast to traditional residue look-up tables which have quadratic growth in spatial complexity. The use of linear arrays of sources and modulators leads to power requirements that also grew linearly with the size of the modulus. Design and demonstration of a proof-of-concept experiment are also presented.