Showing papers on "Gate count published in 1994"

RSYN: a system for automated synthesis of reliable multilevel circuits

Abstract: Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN. >

A systolic, linear-array multiplier for a class of right-shift algorithms

Abstract: A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only upper bound [n]/2 cells are needed for a full n by n multiply. A module-multiplier is then developed by incorporating a Montgomery type of module-reduction. Two such multipliers interconnect to form a purely systolic module exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus. >

Ultrafast Switching with Nonlinear Optics

Abstract: Remember when we optimized our computer programs to minimize the memory usage, even at the expense of readability of the code? Now, with an abundance of memory, we no longer worry about the memory requirements. Remember when we minimized the gate count in a circuit by using techniques such as Karnaugh maps? Now, with VLSI and ULSI chips, gate count is no longer an issue. Yet in telecommunications many applications still need to be optimized to fit within bandwidth limitations. Researchers in optics and photonics dream of making bandwidth an inexpensive, virtually limitless commodity, so that we will be able to tailor applications to optimize their functionality without regard to bandwidth.

Modular 64-bit integer adder

Abstract: A high speed, compact low power integer adder unit for advanced microprocessors features modular construction, low gate count and a fast add time. A 64-bit implementation is characterized by a unique combination of dual rail logic circuits and dual carry select path within each of four 16-bit adder building blocks to achieve a one gate delay increment for each additional 16-bit adder building block after the first. Each of the 16-bit adder building blocks are composed of modules that receive four of sixteen bits of the operands, and each of the modules are comprised of submodules. The submodules are in turn comprised of dual rail logic circuits with a dual carry select path so as to constitute a nested carry select architecture wherein the nesting of the dual carry select path extends from submodules to a module and from modules to a basic building block. The dual carry select paths are optimized both internal to the submodules and modules and at the submodule and module boundaries to achieve a minimum gate delay number.

Cost-performance analysis of FPGA, VLSI and WSI implementations of a RAM-based neural network

Abstract: The paper analyses the hardware implementation of a probabilistic RAM based neural network architecture, named HyperNet in terms of system training speed, size, and component cost. All the systems presented include on-board reinforcement training logic and the necessary control and interface circuitry. Circuit area, gate count, and speed figures are extrapolated from a 10,240 neuron custom VLSI based system constructed at the University of Hertfordshire in 1993. Varying degrees of parallelism, and three implementation technologies are considered. A palm-sized system with a single Xilinx 4025 FPGA serial processor can deliver approximately 800 times the performance of a Sun SPARCstation 10 at a cost of less than #1000. A double Eurocard sized custom VLSI based fully parallel system costs of the order of #10K and offers over five orders of magnitude training speed improvement over a Sun SPARCstation 10.

Optimisation techniques based on the use of genetic algorithms (GAs) for logic implementation on FPGAs

Abstract: The work described in this paper began some time ago as an investigation into two problems associated with logic minimisation or optimisation. These are respectively, the state assignment problem in the design of finite state machines, and the optimisation of combinational logic circuits using Reed-Muller (RM) techniques. When faced with such designs, the use of FPGAs to implement circuits is clearly appropriate. However, because of the limited resources available on FPGA parts, in terms of the number of available CLBs, and the increased difficulty that place and route software will experience in the layout of increasingly complex designs, it is felt that some form of optimisation of the design before implementation is still a necessary stage in the design process. This paper describes the implementation of algorithms which attempt to provide this type of optimisation for the two previously mentioned problems. The resultant software uses genetic algorithms to select, breed and test the fitness of potential solutions, and thereby recommend a near-optimal solution. In practice, these recommended solutions represent a considerable saving (in terms of gate count) on many circuit implementations, as experimental results demonstrate.

Implementation of the arbitrary free-space optical interconnections with equal path lengths by use of a layered structure

Abstract: We describe and demonstrate a scheme to implement arbitrary space-variant optical interconnections with equal path lengths in free-space, using a layered structure for a low gate count and high throughput. We discuss extending the technique to reduce the number of layers by performing small group interconnections on laterally separable locations.

Dual-modulus frequency dividers with minimum gate count

Abstract: A method for minimising the gate count in dual-modulus frequency dividers is presented. The gate count is minimised by identification of a set of Boolean equations with one type of Boolean operator only, using internal gates of D-flipflops to realise the Boolean functions. Circuit diagrams for divide-by-2/3 and divide-by-4/5 static frequency dividers are shown. The minimised circuits have higher speed and lower power consumption compared to conventional solutions because additional gates are not required.

Multigigahertz performance of a superconducting analog-to-digital converter

Abstract: This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.