Showing papers on "Gate count published in 1997"

A fast parallel squarer based on divide-and-conquer

Abstract: Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-/spl mu/m CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation.

High-level area and power estimation for VLSI circuits

Abstract: This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given, multi-output Boolean function description into an equivalent single-output function. The model, is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

High-level area and power estimation for VLSI circuits

Abstract: This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multi-level implementation of the combinational logic. The proposed area model is based on transforming the given multi-output Boolean function description into an equivalent single-output function. The model is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

Development Of A Digital FPLLl ASIC For GA HDTV Receivers

Abstract: We propose a new digital carrier recovery loop architecture for the Grand Alliance high definition television (HDTV) system. We have developed an application specific integrated circuit (ASIC) based on the new architecture. The developed ASIC has a gate count of 60 K with a gate array technology that features 0.5 /spl mu/m, 3.3 V and 2-metal-layer technology. The pull-in range of the proposed architecture is about /spl plusmn/250 kHz with 0 dB carrier-to-noise ratio (CNR).

Design and tuning of FPGA implementations of neural networks

Abstract: Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

Design for testability: today and in the future

Abstract: Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in today's technologies. The Delay Fault models are discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, self-test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular self-testing design techniques are shown. The interaction of testing and synthesis is discussed with a view on delay. Finally, the role of testing is explored in the new design environments which includes Hardware and Software Codesign.

Conflict-free access to multiple single-ported register files

Abstract: Presents a novel static algorithm for mapping values to multiple register files. The algorithm is based on the edge-coloring of a bipartite graph. It at lows the migration of values among the register files to keep the number of RAMs as small as possible. By comparison with the register file design used in the Cydra 5 mini-supercomputer, our approach substantially reduces the number of RAMs. This reduction actually grows with the issue rate. For a system with an issue rate of 6 instructions per cycle, the cost (gate count) of the register files are already cut by half. On a numerical workload like the Livermore Loops, both designs achieve roughly the same performance.

High-Level Design Methodology Overview

Abstract: Major advances in fabrication technology have made possible high-integration, large gate count ASICs. Hardware description languages and logic synthesis have had a significant impact on the design process of these ASICs. With the adoption of HDL-based design, there has emerged a high-level design flow based on synthesis.

A cost-effective morphological filter architecture

Abstract: This paper proposes a new VLSI architecture for morphological filters and presents its design and implementation The proposed architecture can significantly reduce the hardware cost by using a feedback loop path and a decoder/encoder pair comparator The feedback loop path can reuse partial results and the decoder/encoder pair comparator can reduce the gate delay and the gate count especially when the size of the structuring element increases In addition, the proposed architecture requires fewer number of operations and can be easily extended for larger size morphological operations We fabricated the actual chip using the 08 /spl mu/m Samsung/sup TM/ SOG cell library (KG60K) and the total number of gates is only 2,667 The proposed morphological filter chip has been actually fabricated and is running at 30 MHz that meets real-time image processing requirements of the ITU-R BT 601 standard