scispace - formally typeset
Search or ask a question
Topic

Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


Papers
More filters
Proceedings ArticleDOI
23 Jan 2007
TL;DR: A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing and achieves 40% gate count, 51% power consumption and 160% clock frequency comparing to ARM7.
Abstract: A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock frequency comparing to ARM7, even the performance is 67% better in narrow width memory at the same clock frequency. The ARM7 software is also compatible.

5 citations

Proceedings ArticleDOI
15 Jun 2010
TL;DR: This paper presents a proposal of a recovery method for a turn-off failure mode of a laser array on an ORGA and presents its demonstration results.
Abstract: Demand for a large-gate-count robust VLSI chip that is usable in a radiation-rich space environment is increasing daily. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. However, the ORGA has only an unallowable failure mode, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal of a recovery method for a turn-off failure mode of a laser array on an ORGA and presents its demonstration results.

5 citations

01 Jan 2008
TL;DR: In this paper, a dynamically selectable triple modulo redundancy (TMR) architecture is proposed to reduce power consumption when radiation levels are low, which can be applied to mission critical systems for military and aerospace applications.
Abstract: Triple Modulo Redundancy (TMR) is one of the most common techniques for fault mitigation in digital systems. TMR-based computing has a natural application to mission critical systems for military and aerospace applications which are exposed to cosmic radiation and are susceptible to Single Event Upsets (SEUs). TMR's increased immunity to SEUs comes at the expense of increased power consumption and area. This paper presents a dynamically selectable TMR architecture which can be used to reduce power consumption when radiation levels are low. We apply this architecture to a test system in order to evaluate its power reduction and area overhead compared to a traditional static TMR approach. We show that the dynamically selectable TMR can be adopted with only a 2.2% increase in equivalent gate count compared to the traditional static TMR when implemented on a Xilinx Virtex-4 FPGA. This approach yields as much as a 67% reduction in power consumption versus a traditional static TMR approach when radiation levels are low.

5 citations

Proceedings ArticleDOI
04 Mar 1999
TL;DR: A new fault coverage estimation model which can be used in the early stage of VLSI design, an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault Coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/.
Abstract: This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/. The fault coverages using three different testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, I/O count, and FF count. These parameters are often readily available at the early stage of VLSI design. Finally, the composite fault coverage is estimated by combining different fault coverages. Experimental result showed a 1.9% model estimation error with a given circuit information in the early design.

5 citations

Journal ArticleDOI
TL;DR: This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver and obtained low area on chip.
Abstract: Problem statement: Fast Fourier Transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Results: Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted 6691 equivalent gate count and lead us to obtain low area on chip. Conclusion: The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report showed the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz.

5 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
84% related
Electronic circuit
114.2K papers, 971.5K citations
81% related
Integrated circuit
82.7K papers, 1M citations
80% related
Transistor
138K papers, 1.4M citations
79% related
Decoding methods
65.7K papers, 900K citations
77% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847