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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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Book ChapterDOI
07 Mar 2009
TL;DR: This paper presents the first demonstration of a nine-context DORGA architecture and presents experimental results: 1.2-8.97μ s reconfiguration times and 66-221μ s retention times.
Abstract: Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a nine-context DORGA architecture. Furthermore, this paper presents experimental results: 1.2-8.97μ s reconfiguration times and 66-221μ s retention times.

5 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a CDR-less transmission protocol that achieves significant improvements in data rate, reliability, packet security, and power efficiency with respect to state-of-the-art CDRless techniques.
Abstract: Clock and Data Recovery (CDR) has been a foundational receiver component in serial communications. Yet this component is known to add significant design complexity to the receiver and to consume significant resources in area and power. In the resource-limited world of constrained IoT nodes, the need of including CDR in the communication link is being re-assessed and new techniques for achieving reliable serial transmission without CDR have been emerging. These new techniques are distinguished by their use of transition edges rather than bit times for coding and detection. This article presents the design, implementation, and testing of a novel CDR-less transmission protocol that achieves significant improvements in data rate, reliability, packet security, and power efficiency with respect to state-of-the-art CDR-less techniques. The new protocol further tolerates significant jitters and clock discrepancies between transmitter and receiver. An FPGA and an ASIC (65 nm technology) implementation of the protocol have shown it to consume around 19μ W of power at a clock rate of 25 MHz, and to have a small footprint with a gate count of approximately 2,098 gates. In particular, the new protocol reduces area by more than 87% and power by more than 78% in comparison with CDR-based serial bit transfer protocols. Furthermore, the new protocol is shown to be versatile in its applications to available communication media, including wired, wireless, infrared, and human-body channels, under a variety of digital modulation schemes.

5 citations

Proceedings ArticleDOI
01 Jan 2019
TL;DR: A new design to implement programmable Threshold Logic Gate (TLG) using memristors as weights combined with CMOS circuits for threshold control and comparison has been reported.
Abstract: In this paper, a new design to implement programmable Threshold Logic Gate (TLG) using memristors as weights combined with CMOS circuits for threshold control and comparison has been reported. In this design it is possible to program both weights and threshold of the gate that gives greater flexibility in implementing logic functions with minimum gate count. The operation of the gate has been experimentally verified through simulation by implementing some linear threshold logic functions.

5 citations

Proceedings ArticleDOI
15 Feb 1989
TL;DR: In this paper, the authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices.
Abstract: The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors. >

4 citations

01 Jan 2004
TL;DR: Design techniques for time and space optimization of NCL feedback circuits are developed and compared and a 3-Register Stage method is employed to circulate DATA and NULL wavefronts required to realize feedback in 4-bit binary timer case-study.
Abstract: Design techniques for time and space optimization of NCL feedback circuits are developed and compared. First, a 3-Register Stage method is employed to circulate DATA and NULL wavefronts required to realize feedback in 4-bit binary timer case-study. While modular and adaptable, this approach requires a significant gate count to realize the feedback circuit that comprises 75% of the total gates required. The second methodology aims at reducing the feedback overhead by using the statemaintaining capacity inherent with each threshold logic gate’s built-in hysteresis behavior. This methodology employs two characteristics: the circuit preserves its present state; and it keeps track of the number of requests for DATA so that it can determine the appropriate next state. This embedded approach can reduce the feedback gate count by nearly 50% and also DATA-to-DATA cycle time by 31% depending on the feedback scheme used. Finally, the above-explained methodologies are assessed in terms of their design tradeoffs.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847