Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Datapath bitslice technology

Abstract: A method for reducing circuit gate count is disclosed. The method generally comprises the steps of (A) generating a new file from a source file and a parameter file, wherein the source file comprises a first circuit defined in a hardware description language, the new file comprises a second circuit defined in the hardware description language, the parameter file comprises a second clock frequency for the second circuit that is faster than a first clock frequency for the first circuit, and the first circuit is functionally equivalent to the second circuit, (B) generating a first gate count by synthesizing a first design from the source file, (C) generating a second gate count by synthesizing a second design from the new file and (D) generating a statistic by comparing the first gate count to the second gate count.

Premature Ventricular Complex Detection Chip Obtained Using Convolution Neural Network

Abstract: In this work, a very large scale integration chip for arrhythmia detection is proposed. The proposed chip comprises a convolution neural network (CNN) for detecting the abnormal heartbeat of premature ventricular complex (PVC) by using 4-lead electrocardiogram signals. The proposed CNN comprised two convolution layers and one fully connected layer to achieve high-accuracy PVC detection. The detection accuracy of the proposed CNN circuit was 94.94% when implemented in a single chip using TSMC $0.18-\mu\ \mathbf{m}$ complementary metal-oxide-semiconductor processing techniques. The results indicated that the proposed core consumes 3.1-mW power with a clock frequency of 66.6 MHz, and the gate count of the proposed core was 14 K. Thus, the proposed CNN offers high speed, a small area, and high-accuracy PVC detection.

VLSI Implementation of Multi-Channel ECG Lossless Compression System

Abstract: Electrocardiogram (ECG) is used to record the electrical activity of heart. If the instrument monitoring the signal for a long time, it will produce large amount of data. So, the effective lossless ECG compression system can help to reduce the storage space. This brief presents a hardware architecture of multi-channel lossless ECG compression system. The system is based on the algorithm including multi-channel linear prediction and adaptive linear prediction. Also, Golomb rice code (GRC) is used for entropy coding. The hardware implementation has been designed with low hardware complexity usage while using optimum hardware resources. And the architecture can process multiple channels in parallel that can obtain the high throughput. PTB database has been used for verification and testing purposes. This design was implemented in TSMC 180nm. The implementation results show the gate count is 476K and power consumption is $69.18\mu \text{W}$ while working frequency is 1 KHz.

FlexGrip™: A small and high-performance programmable hardware for highly sequential application.

Abstract: Although the state-of-the-art multi-core/many-core processors with SIMD extension are getting powerful enough for full software implementation of highly data-parallel application, highly sequential application still requires dedicated hardware for accelerating its performance because it lacks data-parallelism. In this paper, we propose a novel programmable hardware called FlexGrip™, which aims at software implementation of Context-Adaptive Binary Arithmetic Coder (CABAC) without dedicated hardware. Our evaluation result shows that gate count of FlexGrip is about 359K gates per core, and with two FlexGrips CABAC is decoded at about 50Mbps and about 120mW is consumed if operated at 333MHz.

A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI

Abstract: A Zero-Overhead Dynamic Optically Reconfigurable Gate Array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize a single instruction set computer that requires zero-overhead fast reconfiguration. To date, although the concept and architecture have been proposed and some simulation results of designs have been presented, a ZO-ORGA VLSI chip has never been fabricated. In this paper, the first 1,632 gate-count zero-overhead VLSI chip fabricated using 0.35 um CMOS process technology is presented. The 1,632 ZO-DORGA-VLSI is not only the first prototype VLSI chip; it is also the largest gate-count ORGA. Such a large gate count ORGA had never been fabricated until this study. The performance of ZO-DORGA-VLSI is clarified and discussed using experimental results.