Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

Abstract: Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

Embedded 8-bit AES in wireless Bluetooth application

Abstract: This paper presents an 8-bit AES direct FPGA hardware implementation of CFB/OFB operations without using the Block RAM (BRAM). The 8-bit AES core is then embedded through a microcontroller to interface with Bluetooth wireless for performing encryption or decryption. Two sets of the embedded systems are configured together to experiment the AES operation of the image encryption and decryption through wireless communication achieved the baud rate of 0.23 Megabits per second (Mbps). CFB/OFB operations have two advantages over ECB operation; one is the low area circuit design, and the other is the complete hiding of input patterns in plain image with identical colors. Though CFB/OFB implementation without BRAM has a little larger slice area then the implementation with RAM, yet the non-BRAM in ASIC implementation achieved only 2.2K gates, synthesized using 0.18μm technology, which is the smallest gate count for the 8-bit ASIC implementation ever proposed.

Lightweight mix columns implementation for AES

Abstract: Since the debut of the Advanced Encryption Standard (AES), it has been thoroughly studied by hardware designers with the goal of reducing the area and delay of the hardware implementation of this cryptosystem. This paper proposes an implementation of the AES mix columns operation. In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

Abstract: Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-μm CMOS technology process. The total gate count is 30114 and its layout area is about 710 × 710-μm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.

Comprehensive quantum analysis of existing four variable reversible gates

Abstract: Throughout the last decade, reversible logic has been an emerging research topic. Over the years, a considerable number of application specific new reversible gates with varied characteristics have been proposed. Barring few, most of the gates lack fundamental quantum mapping in contemporary literature. This paper takes into account the four variable reversible gates those have been proposed and provides the Toffoli mapping using positive control lines. The authors optimize the designs using negative control lines wherever possible. The quantum cost, quantum gate count and two-qubit gate count required to implement those reversible gates have been provided which will set a benchmark for optimized gate choice for complex Boolean realizations. The authors also provide Hamming Distance based Complexity analysis.