Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A BCH decoding architecture with mixed parallelization degrees for flash controller applications

Abstract: Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of ECC hardware is taking up a significant share of the overall SOC logic. Scaling ECC strength to growing error correction requirements has become increasingly difficult when considering cost and area limitations. In this work, a new BCH decoding architecture is presented that combines different parallelization degrees for the Berlekamp-Massey algorithm and the Chien search. This approach significantly reduces the number of required multipliers. Nevertheless, the average decoding speed is equal to that of a fully parallel implementation.

Controlled and Uncontrolled SWAP Gates in Reversible Logic Synthesis

Abstract: This paper presents a quantum-level realization and synthesis approach using SWAP and Fredkin (SF) gates. Our quantum realization of negative-controlled Fredkin gate requires five 2-qubit elementary quantum gates, the same as that required for realizing a positive-controlled Fredkin gate. We also propose and evaluate the performance of a synthesis approach using SF gates for realizing conservative reversible functions. Our result shows that circuit realization for conservative function using SF gates is more efficient than Toffoli gates. We achieve up to \(87\%\) improvement in gate count and quantum cost for \((4 \times 4)\) conservative reversible functions.

A Novel 8 Bit Digital Comparator for 3x3 Fixed Kernel based Modified Shear Sorting

Abstract: The need for an optimized area, speed and power plays a vital role for any median filter is good at removing impulse noise without degrading the image details. The main operation of the median is Rank ordering. It is a computationally complex operation, so it is hard to implement it in real time. This paper introduces a new sorting technique called for Snake like sorting. The proposed Sorting technique is implemented as a parallel architecture. This algorithm is a Mesh based sorting that require less number of comparators for rank ordering. The proposed architecture is compared with other Rank Ordering algorithm on the basis of power, speed, and area and found to exhibit good results. The proposed architecture is implemented on parallel and pipelined schemes and is targeted for Spartan 3e Device with gate capacity 5000 using Xilinx 7.1i compiler version. The pipelined scheme has an operating frequency of 81 Mhz occupying 283 slices with a gate count of 5,640.

A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems

Abstract: The paper proposes a programmable geometry engine (GE) reducing the expensive internal buffers and register files of the conventional programmable GEs and sharing the datapaths of a special function unit. The proposed GE is appropriate for the embedded 3D graphics environment where the reduction of hardware cost is a critical issue. The degraded performance caused by the hardware reduction is compensated by a variable write-back timing architecture with a dynamic hazard controller and a data forwarding method. The GE is implemented by a 0.13 /spl mu/m CMOS technology and has the performance of up to 33.2M vertices/sec, which is 1.66 times improvement on previous work. Its equivalent gate count is 206k and operating frequency is 166 MHz.